Lines Matching defs:brg
105 u32 div, brg;
108 brg = mainclk_hz / speed_hz / (4 << div);
109 /* now we have BRG+1 in brg, so count with that */
110 if (brg < (4 + 1)) {
111 brg = (4 + 1); /* speed_hz too big */
112 break; /* set lowest brg (div is == 0) */
114 if (brg <= (63 + 1))
115 break; /* we have valid brg and div */
119 brg = (63 + 1); /* set highest brg and div */
121 brg--;
122 return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
698 /* use minimal allowed brg and div values as initial setting: */
870 * produce valid brg and div