Lines Matching refs:a3700_spi
102 struct a3700_spi {
117 static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset)
119 return readl(a3700_spi->base + offset);
122 static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data)
124 writel(data, a3700_spi->base + offset);
127 static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi)
131 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
133 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
136 static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs)
140 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
142 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
145 static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi,
150 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
152 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
155 static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi,
160 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
177 dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode);
181 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
186 static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi, bool enable)
190 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
195 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
198 static void a3700_spi_mode_set(struct a3700_spi *a3700_spi,
203 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
215 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
218 static void a3700_spi_clock_set(struct a3700_spi *a3700_spi,
224 prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz);
233 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
237 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
240 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG);
242 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);
246 static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len)
250 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
255 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
257 a3700_spi->byte_len = len;
260 static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi)
265 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
267 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
270 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
279 static void a3700_spi_init(struct a3700_spi *a3700_spi)
281 struct spi_master *master = a3700_spi->master;
286 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
288 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
292 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
294 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
297 a3700_spi_auto_cs_unset(a3700_spi);
299 a3700_spi_deactivate_cs(a3700_spi, i);
302 a3700_spi_fifo_mode_set(a3700_spi, true);
305 a3700_spi_mode_set(a3700_spi, master->mode_bits);
308 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
309 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0);
312 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
313 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);
319 struct a3700_spi *a3700_spi;
322 a3700_spi = spi_master_get_devdata(master);
325 cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG);
327 if (!cause || !(a3700_spi->wait_mask & cause))
331 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
332 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);
335 complete(&a3700_spi->done);
342 struct a3700_spi *a3700_spi;
347 a3700_spi = spi_master_get_devdata(spi->master);
355 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
356 if (a3700_spi->wait_mask & ctrl_reg)
359 reinit_completion(&a3700_spi->done);
361 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG,
362 a3700_spi->wait_mask);
365 timeout = wait_for_completion_timeout(&a3700_spi->done,
368 a3700_spi->wait_mask = 0;
381 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
382 if (a3700_spi->wait_mask & ctrl_reg)
385 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
394 struct a3700_spi *a3700_spi;
396 a3700_spi = spi_master_get_devdata(spi->master);
397 a3700_spi->wait_mask = bit_mask;
402 static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi,
407 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
412 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
418 struct a3700_spi *a3700_spi;
420 a3700_spi = spi_master_get_devdata(spi->master);
422 a3700_spi_clock_set(a3700_spi, xfer->speed_hz);
427 a3700_spi_bytelen_set(a3700_spi, 4);
430 a3700_spi->tx_buf = xfer->tx_buf;
431 a3700_spi->rx_buf = xfer->rx_buf;
432 a3700_spi->buf_len = xfer->len;
437 struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master);
440 a3700_spi_activate_cs(a3700_spi, spi->chip_select);
442 a3700_spi_deactivate_cs(a3700_spi, spi->chip_select);
445 static void a3700_spi_header_set(struct a3700_spi *a3700_spi)
451 spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);
452 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);
453 spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);
454 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
457 if (a3700_spi->tx_buf) {
466 addr_cnt = a3700_spi->buf_len % 4;
470 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);
473 a3700_spi->buf_len -= addr_cnt;
478 val = (val << 8) | a3700_spi->tx_buf[0];
479 a3700_spi->tx_buf++;
481 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);
486 static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi)
490 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
494 static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi)
498 while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) {
499 val = *(u32 *)a3700_spi->tx_buf;
500 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
501 a3700_spi->buf_len -= 4;
502 a3700_spi->tx_buf += 4;
508 static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi)
510 u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
515 static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi)
519 while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) {
520 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
521 if (a3700_spi->buf_len >= 4) {
523 memcpy(a3700_spi->rx_buf, &val, 4);
525 a3700_spi->buf_len -= 4;
526 a3700_spi->rx_buf += 4;
533 while (a3700_spi->buf_len) {
534 *a3700_spi->rx_buf = val & 0xff;
537 a3700_spi->buf_len--;
538 a3700_spi->rx_buf++;
546 static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi)
551 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
553 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
556 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
562 a3700_spi_fifo_flush(a3700_spi);
565 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
571 struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
575 ret = clk_enable(a3700_spi->clk);
582 ret = a3700_spi_fifo_flush(a3700_spi);
586 a3700_spi_mode_set(a3700_spi, spi->mode);
595 struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
601 a3700_spi_fifo_mode_set(a3700_spi, true);
605 a3700_spi_fifo_thres_set(a3700_spi, byte_len);
612 a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false);
615 a3700_spi_fifo_flush(a3700_spi);
618 a3700_spi_header_set(a3700_spi);
624 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0);
627 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,
628 a3700_spi->buf_len);
630 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
633 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
636 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
638 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
646 a3700_spi->xmit_data = (a3700_spi->buf_len != 0);
649 while (a3700_spi->buf_len) {
650 if (a3700_spi->tx_buf) {
660 ret = a3700_spi_fifo_write(a3700_spi);
663 } else if (a3700_spi->rx_buf) {
673 ret = a3700_spi_fifo_read(a3700_spi);
691 if (a3700_spi->tx_buf) {
692 if (a3700_spi->xmit_data) {
710 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
712 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
716 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
729 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
733 a3700_spi_transfer_abort_fifo(a3700_spi);
744 struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
748 a3700_spi_fifo_mode_set(a3700_spi, false);
750 while (a3700_spi->buf_len) {
755 if (a3700_spi->buf_len < 4)
756 a3700_spi_bytelen_set(a3700_spi, 1);
758 if (a3700_spi->byte_len == 1)
759 val = *a3700_spi->tx_buf;
761 val = *(u32 *)a3700_spi->tx_buf;
763 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
766 while (!(spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG) &
770 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
772 memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len);
774 a3700_spi->buf_len -= a3700_spi->byte_len;
775 a3700_spi->tx_buf += a3700_spi->byte_len;
776 a3700_spi->rx_buf += a3700_spi->byte_len;
800 struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
802 clk_disable(a3700_spi->clk);
819 struct a3700_spi *spi;
914 struct a3700_spi *spi = spi_master_get_devdata(master);