Lines Matching defs:master
45 static inline u8 amd_spi_readreg8(struct spi_master *master, int idx)
47 struct amd_spi *amd_spi = spi_master_get_devdata(master);
52 static inline void amd_spi_writereg8(struct spi_master *master, int idx,
55 struct amd_spi *amd_spi = spi_master_get_devdata(master);
60 static inline void amd_spi_setclear_reg8(struct spi_master *master, int idx,
63 u8 tmp = amd_spi_readreg8(master, idx);
66 amd_spi_writereg8(master, idx, tmp);
69 static inline u32 amd_spi_readreg32(struct spi_master *master, int idx)
71 struct amd_spi *amd_spi = spi_master_get_devdata(master);
76 static inline void amd_spi_writereg32(struct spi_master *master, int idx,
79 struct amd_spi *amd_spi = spi_master_get_devdata(master);
84 static inline void amd_spi_setclear_reg32(struct spi_master *master, int idx,
87 u32 tmp = amd_spi_readreg32(master, idx);
90 amd_spi_writereg32(master, idx, tmp);
93 static void amd_spi_select_chip(struct spi_master *master)
95 struct amd_spi *amd_spi = spi_master_get_devdata(master);
98 amd_spi_setclear_reg8(master, AMD_SPI_ALT_CS_REG, chip_select,
102 static void amd_spi_clear_fifo_ptr(struct spi_master *master)
104 amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR,
108 static void amd_spi_set_opcode(struct spi_master *master, u8 cmd_opcode)
110 amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, cmd_opcode,
114 static inline void amd_spi_set_rx_count(struct spi_master *master,
117 amd_spi_setclear_reg8(master, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
120 static inline void amd_spi_set_tx_count(struct spi_master *master,
123 amd_spi_setclear_reg8(master, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
146 static void amd_spi_execute_opcode(struct spi_master *master)
148 struct amd_spi *amd_spi = spi_master_get_devdata(master);
151 amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
159 struct spi_master *master = spi->master;
161 amd_spi_clear_fifo_ptr(master);
167 struct spi_master *master,
189 amd_spi_set_opcode(master, cmd_opcode);
198 amd_spi_set_tx_count(master, tx_len);
199 amd_spi_clear_fifo_ptr(master);
201 amd_spi_execute_opcode(master);
210 amd_spi_set_rx_count(master, rx_len);
211 amd_spi_clear_fifo_ptr(master);
213 amd_spi_execute_opcode(master);
216 buf[i] = amd_spi_readreg8(master,
226 spi_finalize_current_message(master);
231 static int amd_spi_master_transfer(struct spi_master *master,
234 struct amd_spi *amd_spi = spi_master_get_devdata(master);
238 amd_spi_select_chip(master);
244 amd_spi_fifo_xfer(amd_spi, master, msg);
257 struct spi_master *master;
263 master = spi_alloc_master(dev, sizeof(struct amd_spi));
264 if (!master) {
265 dev_err(dev, "Error allocating SPI master\n");
269 amd_spi = spi_master_get_devdata(master);
281 master->bus_num = 0;
282 master->num_chipselect = 4;
283 master->mode_bits = 0;
284 master->flags = SPI_MASTER_HALF_DUPLEX;
285 master->setup = amd_spi_master_setup;
286 master->transfer_one_message = amd_spi_master_transfer;
287 master->max_transfer_size = amd_spi_max_transfer_size;
288 master->max_message_size = amd_spi_max_transfer_size;
291 err = devm_spi_register_master(dev, master);
300 spi_master_put(master);