Lines Matching refs:aq
225 static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
227 u32 value = readl_relaxed(aq->regs + offset);
232 dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value,
239 static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
244 dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value,
248 writel_relaxed(value, aq->regs + offset);
300 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
383 if (aq->mr != QSPI_MR_SMM) {
384 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
385 aq->mr = QSPI_MR_SMM;
389 (void)atmel_qspi_read(aq, QSPI_SR);
391 if (aq->caps->has_ricr) {
396 atmel_qspi_write(iar, aq, QSPI_IAR);
398 atmel_qspi_write(icr, aq, QSPI_RICR);
400 atmel_qspi_write(icr, aq, QSPI_WICR);
401 atmel_qspi_write(ifr, aq, QSPI_IFR);
407 atmel_qspi_write(iar, aq, QSPI_IAR);
408 atmel_qspi_write(icr, aq, QSPI_ICR);
409 atmel_qspi_write(ifr, aq, QSPI_IFR);
417 struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
426 if (op->addr.val + op->data.nbytes > aq->mmap_size)
429 err = atmel_qspi_set_cfg(aq, op, &offset);
436 (void)atmel_qspi_read(aq, QSPI_IFR);
440 memcpy_fromio(op->data.buf.in, aq->mem + offset,
443 memcpy_toio(aq->mem + offset, op->data.buf.out,
447 atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
451 sr = atmel_qspi_read(aq, QSPI_SR);
456 reinit_completion(&aq->cmd_completion);
457 aq->pending = sr & QSPI_SR_CMD_COMPLETED;
458 atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IER);
459 if (!wait_for_completion_timeout(&aq->cmd_completion,
462 atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IDR);
481 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
491 src_rate = clk_get_rate(aq->pclk);
500 aq->scr = QSPI_SCR_SCBR(scbr);
501 atmel_qspi_write(aq->scr, aq, QSPI_SCR);
506 static void atmel_qspi_init(struct atmel_qspi *aq)
509 atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
512 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
513 aq->mr = QSPI_MR_SMM;
516 atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
521 struct atmel_qspi *aq = dev_id;
524 status = atmel_qspi_read(aq, QSPI_SR);
525 mask = atmel_qspi_read(aq, QSPI_IMR);
531 aq->pending |= pending;
532 if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
533 complete(&aq->cmd_completion);
541 struct atmel_qspi *aq;
545 ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*aq));
557 aq = spi_controller_get_devdata(ctrl);
559 init_completion(&aq->cmd_completion);
560 aq->pdev = pdev;
564 aq->regs = devm_ioremap_resource(&pdev->dev, res);
565 if (IS_ERR(aq->regs)) {
567 return PTR_ERR(aq->regs);
572 aq->mem = devm_ioremap_resource(&pdev->dev, res);
573 if (IS_ERR(aq->mem)) {
575 return PTR_ERR(aq->mem);
578 aq->mmap_size = resource_size(res);
581 aq->pclk = devm_clk_get(&pdev->dev, "pclk");
582 if (IS_ERR(aq->pclk))
583 aq->pclk = devm_clk_get(&pdev->dev, NULL);
585 if (IS_ERR(aq->pclk)) {
587 return PTR_ERR(aq->pclk);
591 err = clk_prepare_enable(aq->pclk);
597 aq->caps = of_device_get_match_data(&pdev->dev);
598 if (!aq->caps) {
604 if (aq->caps->has_qspick) {
606 aq->qspick = devm_clk_get(&pdev->dev, "qspick");
607 if (IS_ERR(aq->qspick)) {
609 err = PTR_ERR(aq->qspick);
614 err = clk_prepare_enable(aq->qspick);
629 0, dev_name(&pdev->dev), aq);
633 atmel_qspi_init(aq);
642 clk_disable_unprepare(aq->qspick);
644 clk_disable_unprepare(aq->pclk);
652 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
655 atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
656 clk_disable_unprepare(aq->qspick);
657 clk_disable_unprepare(aq->pclk);
664 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
666 clk_disable_unprepare(aq->qspick);
667 clk_disable_unprepare(aq->pclk);
675 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
677 clk_prepare_enable(aq->pclk);
678 clk_prepare_enable(aq->qspick);
680 atmel_qspi_init(aq);
682 atmel_qspi_write(aq->scr, aq, QSPI_SCR);