Lines Matching refs:ctrl
109 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
110 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
130 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
133 struct regmap *wcd_regmap = ctrl->regmap;
150 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
153 struct regmap *wcd_regmap = ctrl->regmap;
170 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
173 *val = readl(ctrl->mmio + reg);
177 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
180 writel(val, ctrl->mmio + reg);
184 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
192 spin_lock_irqsave(&ctrl->comp_lock, flags);
193 ctrl->comp = ∁
194 spin_unlock_irqrestore(&ctrl->comp_lock, flags);
197 ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val);
201 ret = wait_for_completion_timeout(ctrl->comp,
209 spin_lock_irqsave(&ctrl->comp_lock, flags);
210 ctrl->comp = NULL;
211 spin_unlock_irqrestore(&ctrl->comp_lock, flags);
216 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
225 spin_lock_irqsave(&ctrl->comp_lock, flags);
226 ctrl->comp = ∁
227 spin_unlock_irqrestore(&ctrl->comp_lock, flags);
230 ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val);
234 ret = wait_for_completion_timeout(ctrl->comp,
245 ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &val);
250 spin_lock_irqsave(&ctrl->comp_lock, flags);
251 ctrl->comp = NULL;
252 spin_unlock_irqrestore(&ctrl->comp_lock, flags);
257 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
262 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
269 ctrl->status[i] = s;
275 struct qcom_swrm_ctrl *ctrl = dev_id;
279 ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &sts);
282 ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
283 dev_err_ratelimited(ctrl->dev,
286 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
291 schedule_work(&ctrl->slave_work);
298 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, sts);
301 spin_lock_irqsave(&ctrl->comp_lock, flags);
302 if (ctrl->comp)
303 complete(ctrl->comp);
304 spin_unlock_irqrestore(&ctrl->comp_lock, flags);
309 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
314 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
315 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
317 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
320 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 0);
323 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
327 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
329 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
332 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, SWRM_RD_WR_CMD_RETRIES);
335 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
340 if (ctrl->mmio) {
341 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
350 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
360 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
370 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
384 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
387 ctrl->reg_read(ctrl, reg, &val);
389 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
390 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
392 return ctrl->reg_write(ctrl, reg, val);
407 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
416 ret = ctrl->reg_write(ctrl, reg, value);
421 ret = ctrl->reg_write(ctrl, reg, 1);
432 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
435 ctrl->reg_read(ctrl, reg, &val);
442 return ctrl->reg_write(ctrl, reg, val);
458 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
467 pcfg = &ctrl->pconfig[p_rt->num - 1];
477 pcfg = &ctrl->pconfig[i];
498 struct qcom_swrm_ctrl *ctrl =
501 qcom_swrm_get_device_status(ctrl);
502 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
506 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
513 mutex_lock(&ctrl->port_lock);
517 port_mask = &ctrl->dout_port_mask;
519 port_mask = &ctrl->din_port_mask;
525 mutex_unlock(&ctrl->port_lock);
528 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
541 mutex_lock(&ctrl->port_lock);
544 maxport = ctrl->num_dout_ports;
545 port_mask = &ctrl->dout_port_mask;
547 maxport = ctrl->num_din_ports;
548 port_mask = &ctrl->din_port_mask;
556 dev_err(ctrl->dev, "All ports busy\n");
578 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
586 mutex_unlock(&ctrl->port_lock);
595 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
596 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
599 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
602 qcom_swrm_stream_free_ports(ctrl, sruntime);
610 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
611 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
613 qcom_swrm_stream_free_ports(ctrl, sruntime);
614 sdw_stream_remove_master(&ctrl->bus, sruntime);
622 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
624 ctrl->sruntime[dai->id] = stream;
631 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
633 return ctrl->sruntime[dai->id];
639 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
649 ctrl->sruntime[dai->id] = sruntime;
668 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
670 sdw_release_stream(ctrl->sruntime[dai->id]);
671 ctrl->sruntime[dai->id] = NULL;
687 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
689 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
692 struct device *dev = ctrl->dev;
705 if (i < ctrl->num_dout_ports)
719 return devm_snd_soc_register_component(ctrl->dev,
724 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
726 struct device_node *np = ctrl->dev->of_node;
733 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
735 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
736 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
742 if (val > ctrl->num_din_ports)
745 ctrl->num_din_ports = val;
751 if (val > ctrl->num_dout_ports)
754 ctrl->num_dout_ports = val;
756 nports = ctrl->num_dout_ports + ctrl->num_din_ports;
776 ctrl->pconfig[i].si = si[i];
777 ctrl->pconfig[i].off1 = off1[i];
778 ctrl->pconfig[i].off2 = off2[i];
779 ctrl->pconfig[i].bp_mode = bp_mode[i];
790 struct qcom_swrm_ctrl *ctrl;
795 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
796 if (!ctrl)
800 ctrl->rows_index = sdw_find_row_index(data->default_rows);
801 ctrl->cols_index = sdw_find_col_index(data->default_cols);
807 ctrl->reg_read = qcom_swrm_ahb_reg_read;
808 ctrl->reg_write = qcom_swrm_ahb_reg_write;
809 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
810 if (!ctrl->regmap)
813 ctrl->reg_read = qcom_swrm_cpu_reg_read;
814 ctrl->reg_write = qcom_swrm_cpu_reg_write;
815 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
816 if (IS_ERR(ctrl->mmio))
817 return PTR_ERR(ctrl->mmio);
820 ctrl->irq = of_irq_get(dev->of_node, 0);
821 if (ctrl->irq < 0) {
822 ret = ctrl->irq;
826 ctrl->hclk = devm_clk_get(dev, "iface");
827 if (IS_ERR(ctrl->hclk)) {
828 ret = PTR_ERR(ctrl->hclk);
832 clk_prepare_enable(ctrl->hclk);
834 ctrl->dev = dev;
835 dev_set_drvdata(&pdev->dev, ctrl);
836 spin_lock_init(&ctrl->comp_lock);
837 mutex_init(&ctrl->port_lock);
838 INIT_WORK(&ctrl->slave_work, qcom_swrm_slave_wq);
840 ctrl->bus.ops = &qcom_swrm_ops;
841 ctrl->bus.port_ops = &qcom_swrm_port_ops;
842 ctrl->bus.compute_params = &qcom_swrm_compute_params;
844 ret = qcom_swrm_get_port_config(ctrl);
848 params = &ctrl->bus.params;
853 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
857 prop = &ctrl->bus.prop;
865 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
867 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
871 "soundwire", ctrl);
877 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
884 qcom_swrm_init(ctrl);
885 ret = qcom_swrm_register_dais(ctrl);
890 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
891 ctrl->version & 0xffff);
896 sdw_bus_master_delete(&ctrl->bus);
898 clk_disable_unprepare(ctrl->hclk);
905 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
907 sdw_bus_master_delete(&ctrl->bus);
908 clk_disable_unprepare(ctrl->hclk);