Lines Matching refs:pdi
676 * WORKAROUND: on all existing Intel controllers, pdi
678 * supports 8 channels. Performing hardcoding for pdi
696 struct sdw_cdns_pdi *pdi,
703 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
704 ch_count += pdi->ch_count;
705 pdi++;
737 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
744 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
745 if (pdi->num >= 2)
746 pdi->intel_alh_id += 2;
752 if (pdi->type != SDW_STREAM_PCM)
755 if (pdi->dir == SDW_DATA_DIR_RX)
760 u32p_replace_bits(&pdi_conf, pdi->intel_alh_id, SDW_SHIM_PCMSYCM_STREAM);
761 u32p_replace_bits(&pdi_conf, pdi->l_ch_num, SDW_SHIM_PCMSYCM_LCHN);
762 u32p_replace_bits(&pdi_conf, pdi->h_ch_num, SDW_SHIM_PCMSYCM_HCHN);
764 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
768 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
775 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
776 if (pdi->num >= 2)
777 pdi->intel_alh_id += 2;
780 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
783 u32p_replace_bits(&conf, pdi->ch_count - 1, SDW_ALH_STRMZCFG_CHN);
785 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
913 struct sdw_cdns_pdi *pdi;
934 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
936 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id);
938 if (!pdi) {
944 intel_pdi_shim_configure(sdw, pdi);
945 intel_pdi_alh_configure(sdw, pdi);
946 sdw_cdns_config_stream(cdns, ch, dir, pdi);
948 /* store pdi and hw_params, may be needed in prepare step */
950 dma->pdi = pdi;
956 pdi->intel_alh_id);
979 pconfig->num = pdi->num;
1026 intel_pdi_shim_configure(sdw, dma->pdi);
1027 intel_pdi_alh_configure(sdw, dma->pdi);
1028 sdw_cdns_config_stream(cdns, ch, dir, dma->pdi);
1034 dma->pdi->intel_alh_id);
1072 dma->pdi = NULL;