Lines Matching refs:pmc
3 * drivers/soc/tegra/pmc.c
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
49 #include <soc/tegra/pmc.h>
55 #include <dt-bindings/soc/tegra-pmc.h>
236 struct tegra_pmc *pmc;
314 void (*init)(struct tegra_pmc *pmc);
315 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
320 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
410 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
421 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
425 if (pmc->tz_only) {
429 if (pmc->dev)
430 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
440 return readl(pmc->base + offset);
443 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
448 if (pmc->tz_only) {
452 if (pmc->dev)
453 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
460 writel(value, pmc->base + offset);
464 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
466 if (pmc->tz_only)
467 return tegra_pmc_readl(pmc, offset);
469 return readl(pmc->scratch + offset);
472 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
475 if (pmc->tz_only)
476 tegra_pmc_writel(pmc, value, offset);
478 writel(value, pmc->scratch + offset);
488 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
489 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
491 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
494 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
496 return (pmc->soc && pmc->soc->powergates[id]);
499 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
501 return test_bit(id, pmc->powergates_available);
504 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
508 if (!pmc || !pmc->soc || !name)
511 for (i = 0; i < pmc->soc->num_powergates; i++) {
512 if (!tegra_powergate_is_valid(pmc, i))
515 if (!strcmp(name, pmc->soc->powergates[i]))
522 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
535 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
545 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
547 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
550 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
557 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
562 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
565 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
581 * @pmc: power management controller
585 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
590 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
593 mutex_lock(&pmc->powergates_lock);
596 mutex_unlock(&pmc->powergates_lock);
600 err = pmc->soc->powergate_set(pmc, id, new_state);
602 mutex_unlock(&pmc->powergates_lock);
607 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
612 mutex_lock(&pmc->powergates_lock);
619 if (pmc->soc->has_gpu_clamps) {
620 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
636 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
639 mutex_unlock(&pmc->powergates_lock);
688 err = tegra_powergate_set(pg->pmc, pg->id, true);
700 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
712 if (pg->pmc->soc->needs_mbist_war)
727 tegra_powergate_set(pg->pmc, pg->id, false);
752 err = tegra_powergate_set(pg->pmc, pg->id, false);
773 struct device *dev = pg->pmc->dev;
792 struct device *dev = pg->pmc->dev;
817 if (!tegra_powergate_is_available(pmc, id))
820 return tegra_powergate_set(pmc, id, true);
830 if (!tegra_powergate_is_available(pmc, id))
833 return tegra_powergate_set(pmc, id, false);
839 * @pmc: power management controller
842 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
844 if (!tegra_powergate_is_valid(pmc, id))
856 if (!tegra_powergate_is_available(pmc, id))
859 return __tegra_powergate_remove_clamping(pmc, id);
877 if (!tegra_powergate_is_available(pmc, id))
888 pg->pmc = pmc;
892 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
903 * @pmc: power management controller
909 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
912 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
913 return pmc->soc->cpu_powergates[cpuid];
926 id = tegra_get_cpu_powergate_id(pmc, cpuid);
930 return tegra_powergate_is_powered(pmc, id);
941 id = tegra_get_cpu_powergate_id(pmc, cpuid);
945 return tegra_powergate_set(pmc, id, true);
956 id = tegra_get_cpu_powergate_id(pmc, cpuid);
969 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
983 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
986 value = tegra_pmc_readl(pmc, PMC_CNTRL);
988 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1006 for (i = 0; i < pmc->soc->num_powergates; i++) {
1007 status = tegra_powergate_is_powered(pmc, i);
1011 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1022 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
1024 if (!pmc->debugfs)
1069 struct device *dev = pg->pmc->dev;
1104 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1106 struct device *dev = pmc->dev;
1115 id = tegra_powergate_lookup(pmc, np->name);
1126 clear_bit(id, pmc->powergates_available);
1132 pg->pmc = pmc;
1134 off = !tegra_powergate_is_powered(pmc, pg->id);
1186 set_bit(id, pmc->powergates_available);
1194 static int tegra_powergate_init(struct tegra_pmc *pmc,
1205 err = tegra_powergate_add(pmc, child);
1228 set_bit(pg->id, pmc->powergates_available);
1256 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1260 for (i = 0; i < pmc->soc->num_io_pads; i++)
1261 if (pmc->soc->io_pads[i].id == id)
1262 return &pmc->soc->io_pads[i];
1267 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1275 pad = tegra_io_pad_find(pmc, id);
1277 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1287 *status = pmc->soc->regs->dpd_status;
1288 *request = pmc->soc->regs->dpd_req;
1290 *status = pmc->soc->regs->dpd2_status;
1291 *request = pmc->soc->regs->dpd2_req;
1297 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1304 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1308 if (pmc->clk) {
1309 rate = pmc->rate;
1311 dev_err(pmc->dev, "failed to get clock rate\n");
1315 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1320 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1326 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1334 value = tegra_pmc_readl(pmc, offset);
1344 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1346 if (pmc->clk)
1347 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1362 mutex_lock(&pmc->powergates_lock);
1364 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1366 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1370 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1372 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1374 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1378 tegra_io_pad_unprepare(pmc);
1381 mutex_unlock(&pmc->powergates_lock);
1398 mutex_lock(&pmc->powergates_lock);
1400 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1402 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1406 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1408 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1410 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1414 tegra_io_pad_unprepare(pmc);
1417 mutex_unlock(&pmc->powergates_lock);
1422 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1428 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1433 value = tegra_pmc_readl(pmc, status);
1438 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1444 pad = tegra_io_pad_find(pmc, id);
1451 mutex_lock(&pmc->powergates_lock);
1453 if (pmc->soc->has_impl_33v_pwr) {
1454 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1461 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1464 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1466 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1469 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1476 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1479 mutex_unlock(&pmc->powergates_lock);
1486 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1491 pad = tegra_io_pad_find(pmc, id);
1498 if (pmc->soc->has_impl_33v_pwr)
1499 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1501 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1536 return pmc->suspend_mode;
1544 pmc->suspend_mode = mode;
1559 rate = pmc->rate;
1569 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1571 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1573 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1575 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1577 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1580 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1584 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1592 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1596 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1600 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1604 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1609 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1612 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1614 pmc->cpu_good_time = value;
1617 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1619 pmc->cpu_off_time = value;
1623 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1625 pmc->core_osc_time = values[0];
1626 pmc->core_pmu_time = values[1];
1629 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1631 pmc->core_off_time = value;
1633 pmc->corereq_high = of_property_read_bool(np,
1636 pmc->sysclkreq_high = of_property_read_bool(np,
1639 pmc->combined_req = of_property_read_bool(np,
1642 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1647 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1648 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1650 pmc->lp0_vec_phys = values[0];
1651 pmc->lp0_vec_size = values[1];
1656 static void tegra_pmc_init(struct tegra_pmc *pmc)
1658 if (pmc->soc->init)
1659 pmc->soc->init(pmc);
1662 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1666 struct device *dev = pmc->dev;
1670 if (!pmc->soc->has_tsense_reset)
1673 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1702 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1704 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1708 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1726 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1728 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1730 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1732 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1740 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1742 return pmc->soc->num_io_pads;
1748 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1750 return pmc->soc->io_pads[group].name;
1758 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1760 *pins = &pmc->soc->io_pads[group].id;
1778 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1783 pad = tegra_io_pad_find(pmc, pin);
1789 ret = tegra_io_pad_get_voltage(pmc, pad->id);
1797 ret = tegra_io_pad_is_powered(pmc, pad->id);
1817 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1824 pad = tegra_io_pad_find(pmc, pin);
1845 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
1868 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
1872 if (!pmc->soc->num_pin_descs)
1875 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
1876 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
1877 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
1879 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
1880 pmc);
1881 if (IS_ERR(pmc->pctl_dev)) {
1882 err = PTR_ERR(pmc->pctl_dev);
1883 dev_err(pmc->dev, "failed to register pin controller: %d\n",
1896 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1897 value &= pmc->soc->regs->rst_source_mask;
1898 value >>= pmc->soc->regs->rst_source_shift;
1900 if (WARN_ON(value >= pmc->soc->num_reset_sources))
1903 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
1913 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1914 value &= pmc->soc->regs->rst_level_mask;
1915 value >>= pmc->soc->regs->rst_level_shift;
1917 if (WARN_ON(value >= pmc->soc->num_reset_levels))
1920 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
1925 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
1927 struct device *dev = pmc->dev;
1930 if (pmc->soc->reset_sources) {
1938 if (pmc->soc->reset_levels) {
1964 struct tegra_pmc *pmc = domain->host_data;
1965 const struct tegra_pmc_soc *soc = pmc->soc;
1984 &pmc->irq, pmc);
1988 spec.fwnode = &pmc->dev->of_node->fwnode;
2007 &pmc->irq, pmc);
2031 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2039 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2040 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2042 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2043 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2051 value = tegra_pmc_readl(pmc, offset);
2058 tegra_pmc_writel(pmc, value, offset);
2065 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2077 value = tegra_pmc_readl(pmc, offset);
2098 tegra_pmc_writel(pmc, value, offset);
2105 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2113 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2116 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2123 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2126 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2133 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2136 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2157 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2190 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2195 np = of_irq_find_parent(pmc->dev->of_node);
2204 pmc->irq.name = dev_name(pmc->dev);
2205 pmc->irq.irq_mask = tegra_irq_mask_parent;
2206 pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2207 pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2208 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2209 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2210 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2212 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2213 &tegra_pmc_irq_domain_ops, pmc);
2214 if (!pmc->domain) {
2215 dev_err(pmc->dev, "failed to allocate domain\n");
2225 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2230 mutex_lock(&pmc->powergates_lock);
2234 pmc->rate = data->new_rate;
2238 mutex_unlock(&pmc->powergates_lock);
2251 tegra_pmc_readl(pmc, offset);
2252 /* pmc clk propagation delay 2 us */
2261 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2272 val = tegra_pmc_readl(pmc, clk->offs);
2275 tegra_pmc_writel(pmc, val, clk->offs);
2286 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2295 val = tegra_pmc_readl(pmc, offs);
2297 tegra_pmc_writel(pmc, val, offs);
2327 tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2334 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2357 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2383 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2390 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2407 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2415 num_clks = pmc->soc->num_pmc_clks;
2416 if (pmc->soc->has_blink_output)
2422 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2426 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2436 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2439 data = pmc->soc->pmc_clks_data + i;
2441 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2443 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2450 dev_warn(pmc->dev,
2459 if (pmc->soc->has_blink_output) {
2460 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2461 clk = tegra_pmc_clk_gate_register(pmc,
2467 dev_warn(pmc->dev,
2473 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2478 dev_warn(pmc->dev,
2486 dev_warn(pmc->dev,
2497 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2512 if (WARN_ON(!pmc->base || !pmc->soc))
2515 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2527 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2528 if (IS_ERR(pmc->wake))
2529 return PTR_ERR(pmc->wake);
2531 pmc->wake = base;
2536 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2537 if (IS_ERR(pmc->aotag))
2538 return PTR_ERR(pmc->aotag);
2540 pmc->aotag = base;
2545 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2546 if (IS_ERR(pmc->scratch))
2547 return PTR_ERR(pmc->scratch);
2549 pmc->scratch = base;
2552 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2553 if (IS_ERR(pmc->clk)) {
2554 err = PTR_ERR(pmc->clk);
2561 pmc->clk = NULL;
2569 if (pmc->clk) {
2570 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2571 err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
2578 pmc->rate = clk_get_rate(pmc->clk);
2581 pmc->dev = &pdev->dev;
2583 tegra_pmc_init(pmc);
2585 tegra_pmc_init_tsense_reset(pmc);
2587 tegra_pmc_reset_sysfs_init(pmc);
2602 err = tegra_pmc_pinctrl_init(pmc);
2606 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2610 err = tegra_pmc_irq_init(pmc);
2614 mutex_lock(&pmc->powergates_lock);
2615 iounmap(pmc->base);
2616 pmc->base = base;
2617 mutex_unlock(&pmc->powergates_lock);
2619 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
2620 platform_set_drvdata(pdev, pmc);
2629 debugfs_remove(pmc->debugfs);
2633 clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
2641 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2643 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2650 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2652 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2684 static void tegra20_pmc_init(struct tegra_pmc *pmc)
2689 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2691 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2693 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2695 if (pmc->sysclkreq_high)
2700 if (pmc->corereq_high)
2706 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2709 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2711 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2714 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
2715 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
2716 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
2717 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
2718 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
2720 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
2724 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2730 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2737 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3186 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3197 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3205 dev_err(pmc->dev, "failed to map PMC wake registers\n");
3480 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3481 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3482 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3483 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3484 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3485 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3486 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3487 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3488 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3494 .name = "tegra-pmc",
3505 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
3509 saved = readl(pmc->base + pmc->soc->regs->scratch0);
3516 writel(value, pmc->base + pmc->soc->regs->scratch0);
3517 value = readl(pmc->base + pmc->soc->regs->scratch0);
3526 writel(saved, pmc->base + pmc->soc->regs->scratch0);
3543 mutex_init(&pmc->powergates_lock);
3584 pmc->base = ioremap(regs.start, resource_size(®s));
3585 if (!pmc->base) {
3592 pmc->soc = match->data;
3594 if (pmc->soc->maybe_tz_only)
3595 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
3598 for (i = 0; i < pmc->soc->num_powergates; i++)
3599 if (pmc->soc->powergates[i])
3600 set_bit(i, pmc->powergates_available);
3608 pmc->soc->setup_irq_polarity(pmc, np, invert);