Lines Matching defs:value
443 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
450 value, 0, 0, 0, 0, &res);
460 writel(value, pmc->base + offset);
472 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
476 tegra_pmc_writel(pmc, value, offset);
478 writel(value, pmc->scratch + offset);
967 u32 value;
969 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
970 value &= ~PMC_SCRATCH0_MODE_MASK;
974 value |= PMC_SCRATCH0_MODE_RECOVERY;
977 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
980 value |= PMC_SCRATCH0_MODE_RCM;
983 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
986 value = tegra_pmc_readl(pmc, PMC_CNTRL);
987 value |= PMC_CNTRL_MAIN_RST;
988 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1301 unsigned long rate, value;
1318 value = DIV_ROUND_UP(1000000000, rate);
1319 value = DIV_ROUND_UP(200, value);
1320 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1329 u32 value;
1334 value = tegra_pmc_readl(pmc, offset);
1335 if ((value & mask) == val)
1425 u32 mask, value;
1433 value = tegra_pmc_readl(pmc, status);
1435 return !(value & mask);
1442 u32 value;
1454 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1457 value &= ~BIT(pad->voltage);
1459 value |= BIT(pad->voltage);
1461 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1464 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1465 value |= BIT(pad->voltage);
1466 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1469 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1472 value &= ~BIT(pad->voltage);
1474 value |= BIT(pad->voltage);
1476 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1489 u32 value;
1499 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1501 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1503 if ((value & BIT(pad->voltage)) == 0)
1551 u32 value;
1577 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1578 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1579 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1580 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1586 u32 value, values[2];
1588 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1590 switch (value) {
1611 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1614 pmc->cpu_good_time = value;
1616 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1619 pmc->cpu_off_time = value;
1628 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1631 pmc->core_off_time = value;
1668 u32 value, checksum;
1702 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1703 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1704 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1706 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1708 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1710 value = PMC_SCRATCH55_RESET_TEGRA;
1711 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1712 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1713 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1719 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1720 + ((value >> 24) & 0xff);
1724 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1726 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1728 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1729 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1730 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1894 u32 value;
1896 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1897 value &= pmc->soc->regs->rst_source_mask;
1898 value >>= pmc->soc->regs->rst_source_shift;
1900 if (WARN_ON(value >= pmc->soc->num_reset_sources))
1903 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
1911 u32 value;
1913 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1914 value &= pmc->soc->regs->rst_level_mask;
1915 value >>= pmc->soc->regs->rst_level_shift;
1917 if (WARN_ON(value >= pmc->soc->num_reset_levels))
1920 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
2033 u32 value;
2051 value = tegra_pmc_readl(pmc, offset);
2054 value |= BIT(bit);
2056 value &= ~BIT(bit);
2058 tegra_pmc_writel(pmc, value, offset);
2067 u32 value;
2077 value = tegra_pmc_readl(pmc, offset);
2082 value |= BIT(bit);
2087 value &= ~BIT(bit);
2091 value ^= BIT(bit);
2098 tegra_pmc_writel(pmc, value, offset);
2107 u32 value;
2116 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2119 value &= ~(1 << bit);
2121 value |= 1 << bit;
2123 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2134 u32 value;
2136 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2141 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2146 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2150 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2157 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2567 * CLK notifier, hence we're caching the rate's value locally.
2686 u32 value, osc, pmu, off;
2689 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2690 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2691 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2693 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2696 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
2698 value |= PMC_CNTRL_SYSCLK_POLARITY;
2701 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
2703 value |= PMC_CNTRL_PWRREQ_POLARITY;
2706 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2709 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2710 value |= PMC_CNTRL_SYSCLK_OE;
2711 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2728 u32 value;
2730 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2733 value |= PMC_CNTRL_INTR_POLARITY;
2735 value &= ~PMC_CNTRL_INTR_POLARITY;
2737 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3192 u32 value;
3209 value = readl(wake + WAKE_AOWAKE_CTRL);
3212 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3214 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3216 writel(value, wake + WAKE_AOWAKE_CTRL);
3507 u32 value, saved;
3510 value = saved ^ 0xffffffff;
3512 if (value == 0xffffffff)
3513 value = 0xdeadbeef;
3516 writel(value, pmc->base + pmc->soc->regs->scratch0);
3517 value = readl(pmc->base + pmc->soc->regs->scratch0);
3520 if (value == 0) {
3525 /* restore original value */