Lines Matching refs:wrp
1067 int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
1068 int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
1095 int (*init_reg_clock)(struct pmic_wrapper *wrp);
1096 int (*init_soc_specific)(struct pmic_wrapper *wrp);
1099 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
1101 return readl(wrp->base + wrp->master->regs[reg]);
1104 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
1106 writel(val, wrp->base + wrp->master->regs[reg]);
1109 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
1111 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1116 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
1118 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1131 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
1133 if (pwrap_is_fsm_vldclr(wrp))
1134 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1137 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
1139 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
1142 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
1144 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1150 static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
1159 return fp(wrp) ? 0 : -ETIMEDOUT;
1160 if (fp(wrp))
1165 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1169 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1171 pwrap_leave_fsm_vldclr(wrp);
1175 pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
1177 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
1181 *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
1183 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1188 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1194 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1196 pwrap_leave_fsm_vldclr(wrp);
1200 pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
1203 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
1207 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
1210 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1216 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1218 return wrp->slave->pwrap_read(wrp, adr, rdata);
1221 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1225 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1227 pwrap_leave_fsm_vldclr(wrp);
1231 pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
1237 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1242 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1244 pwrap_leave_fsm_vldclr(wrp);
1248 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
1260 pwrap_read(wrp, adr, &rdata);
1266 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1268 return wrp->slave->pwrap_write(wrp, adr, wdata);
1281 static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
1285 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
1286 pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
1287 pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
1288 pwrap_writel(wrp, 1, PWRAP_MAN_EN);
1289 pwrap_writel(wrp, 0, PWRAP_DIO_EN);
1291 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
1293 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1295 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
1299 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1302 ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
1304 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1308 pwrap_writel(wrp, 0, PWRAP_MAN_EN);
1309 pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
1320 static int pwrap_init_sidly(struct pmic_wrapper *wrp)
1330 pwrap_writel(wrp, i, PWRAP_SIDLY);
1331 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
1334 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
1340 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
1345 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
1350 static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
1356 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
1359 ret = pwrap_wait_for_state(wrp,
1362 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1366 pwrap_writel(wrp, 1, PWRAP_DIO_EN);
1369 pwrap_read(wrp,
1370 wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
1372 dev_err(wrp->dev,
1385 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
1394 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
1395 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
1402 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
1403 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
1406 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
1408 switch (wrp->master->type) {
1410 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
1413 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
1414 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
1423 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
1425 switch (wrp->slave->type) {
1427 pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
1428 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
1432 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
1433 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
1435 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
1444 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
1446 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
1449 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
1454 ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
1462 static int pwrap_init_cipher(struct pmic_wrapper *wrp)
1467 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
1468 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
1469 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
1470 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
1472 switch (wrp->master->type) {
1474 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
1475 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
1483 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
1486 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
1493 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
1494 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
1495 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
1496 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
1498 switch (wrp->slave->type) {
1500 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
1502 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
1508 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
1516 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
1518 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
1523 ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
1525 dev_err(wrp->dev,
1531 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
1532 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
1534 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
1538 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
1541 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1543 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1546 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
1553 static int pwrap_init_security(struct pmic_wrapper *wrp)
1558 ret = pwrap_init_cipher(wrp);
1563 if (pwrap_write(wrp,
1564 wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
1567 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
1568 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
1569 pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
1571 pwrap_writel(wrp,
1572 wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1577 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
1580 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
1581 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
1582 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
1583 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
1584 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
1585 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
1586 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
1587 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
1588 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
1591 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1593 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1595 dev_err(wrp->dev, "enable dewrap fail\n");
1602 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
1605 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1607 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1609 dev_err(wrp->dev, "enable dewrap fail\n");
1616 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
1619 switch (wrp->slave->type) {
1621 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
1622 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
1623 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
1624 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
1625 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
1634 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
1636 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
1638 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
1643 static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
1645 pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
1647 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
1648 pwrap_writel(wrp, 1, PWRAP_CRC_EN);
1649 pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
1650 pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
1652 pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
1653 pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
1654 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
1655 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
1660 static int pwrap_init(struct pmic_wrapper *wrp)
1664 if (wrp->rstc)
1665 reset_control_reset(wrp->rstc);
1666 if (wrp->rstc_bridge)
1667 reset_control_reset(wrp->rstc_bridge);
1669 if (wrp->master->type == PWRAP_MT8173) {
1671 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
1672 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1675 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1677 ret = pwrap_reset_spislave(wrp);
1682 pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
1684 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1686 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
1688 ret = wrp->master->init_reg_clock(wrp);
1692 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1694 ret = pwrap_init_sidly(wrp);
1699 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
1701 ret = pwrap_init_dual_io(wrp);
1706 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
1708 ret = pwrap_init_security(wrp);
1713 if (wrp->master->type == PWRAP_MT8135)
1714 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
1716 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
1717 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
1718 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
1719 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
1720 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
1722 if (wrp->master->init_soc_specific) {
1723 ret = wrp->master->init_soc_specific(wrp);
1729 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
1730 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
1731 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
1733 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
1734 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
1735 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
1744 struct pmic_wrapper *wrp = dev_id;
1746 rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
1747 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
1748 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
1750 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
1751 rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);
1752 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
1753 pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR);
2025 struct pmic_wrapper *wrp;
2038 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
2039 if (!wrp)
2042 platform_set_drvdata(pdev, wrp);
2044 wrp->master = of_device_get_match_data(&pdev->dev);
2045 wrp->slave = of_slave_id->data;
2046 wrp->dev = &pdev->dev;
2049 wrp->base = devm_ioremap_resource(wrp->dev, res);
2050 if (IS_ERR(wrp->base))
2051 return PTR_ERR(wrp->base);
2053 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
2054 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
2055 if (IS_ERR(wrp->rstc)) {
2056 ret = PTR_ERR(wrp->rstc);
2057 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
2062 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
2065 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
2066 if (IS_ERR(wrp->bridge_base))
2067 return PTR_ERR(wrp->bridge_base);
2069 wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
2071 if (IS_ERR(wrp->rstc_bridge)) {
2072 ret = PTR_ERR(wrp->rstc_bridge);
2073 dev_dbg(wrp->dev,
2079 wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
2080 if (IS_ERR(wrp->clk_spi)) {
2081 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2082 PTR_ERR(wrp->clk_spi));
2083 return PTR_ERR(wrp->clk_spi);
2086 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
2087 if (IS_ERR(wrp->clk_wrap)) {
2088 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2089 PTR_ERR(wrp->clk_wrap));
2090 return PTR_ERR(wrp->clk_wrap);
2093 ret = clk_prepare_enable(wrp->clk_spi);
2097 ret = clk_prepare_enable(wrp->clk_wrap);
2102 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
2103 pwrap_writel(wrp, 1, PWRAP_DCM_EN);
2104 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
2111 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
2112 ret = pwrap_init(wrp);
2114 dev_dbg(wrp->dev, "init failed with %d\n", ret);
2119 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
2120 dev_dbg(wrp->dev, "initialization isn't finished\n");
2126 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
2131 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
2132 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
2133 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
2135 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
2136 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
2141 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
2142 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
2145 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
2147 "mt-pmic-pwrap", wrp);
2151 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
2152 if (IS_ERR(wrp->regmap)) {
2153 ret = PTR_ERR(wrp->regmap);
2157 ret = of_platform_populate(np, NULL, NULL, wrp->dev);
2159 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
2167 clk_disable_unprepare(wrp->clk_wrap);
2169 clk_disable_unprepare(wrp->clk_spi);