Lines Matching refs:GPC_PGC_CTRL
98 #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
99 #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
159 regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
189 regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
263 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI),
265 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE),
267 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC),
411 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI),
413 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1),
415 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG1),
417 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG2),
419 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DDR1),
421 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_GPU),
423 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_VPU),
425 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DISP),
427 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI1),
429 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI2),
431 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE2),