Lines Matching defs:config
351 * and including 'mc' fits within a cacheline (yay!). The 'config' part
602 const struct qm_portal_config *config,
987 /* probing time config params for cpu-affine portals */
988 const struct qm_portal_config *config;
1023 affine_portals[i]->config->channel == channel)
1241 * config, everything that follows depends on it and "config" is more
1328 portal->config = c;
1393 pcfg = qm->config;
1403 qm->config = NULL;
1412 pcfg = qm->config;
1464 dev_crit(p->config->dev, "QUERYCONGESTION timeout\n");
1733 cpu = portal->config->cpu;
1749 return (!device_link_add(dev, p->config->dev,
1765 pools &= p->config->pools;
1912 phys_fq = dma_map_single(p->config->dev, fq,
1914 if (dma_mapping_error(p->config->dev, phys_fq)) {
1915 dev_err(p->config->dev, "dma_mapping failed\n");
1932 qm_fqd_set_destwq(&mcc->initfq.fqd, p->config->channel, wq);
1936 dev_err(p->config->dev, "MCR timeout\n");
1990 dev_err(p->config->dev, "ALTER_SCHED timeout\n");
2033 dev_crit(p->config->dev, "ALTER_RETIRE timeout\n");
2199 dev_err(p->config->dev, "QUERY_CGR failed: %s\n",
2384 #define PORTAL_IDX(n) (n->config->channel - QM_CHANNEL_SWPORTAL0)
2442 cgr->chan = p->config->channel;
2472 dev_err(p->config->dev, "CGR HW state partially modified\n");
2495 if (cgr->chan != p->config->channel) {
2497 dev_err(p->config->dev, "CGR not owned by current portal");
2498 dev_dbg(p->config->dev, " create 0x%x, delete 0x%x\n",
2499 cgr->chan, p->config->channel);
2629 dev = p->config->dev;
2832 return portal->config;