Lines Matching refs:pmu
17 #include <linux/soc/dove/pmu.h>
50 struct pmu_data *pmu = rcdev_to_pmu(rc);
54 spin_lock_irqsave(&pmu->lock, flags);
55 val = readl_relaxed(pmu->pmc_base + PMC_SW_RST);
56 writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST);
57 writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST);
58 spin_unlock_irqrestore(&pmu->lock, flags);
65 struct pmu_data *pmu = rcdev_to_pmu(rc);
69 spin_lock_irqsave(&pmu->lock, flags);
70 val &= readl_relaxed(pmu->pmc_base + PMC_SW_RST);
71 writel_relaxed(val, pmu->pmc_base + PMC_SW_RST);
72 spin_unlock_irqrestore(&pmu->lock, flags);
79 struct pmu_data *pmu = rcdev_to_pmu(rc);
83 spin_lock_irqsave(&pmu->lock, flags);
84 val |= readl_relaxed(pmu->pmc_base + PMC_SW_RST);
85 writel_relaxed(val, pmu->pmc_base + PMC_SW_RST);
86 spin_unlock_irqrestore(&pmu->lock, flags);
103 static void __init pmu_reset_init(struct pmu_data *pmu)
107 pmu->reset = pmu_reset;
108 pmu->reset.of_node = pmu->of_node;
110 ret = reset_controller_register(&pmu->reset);
112 pr_err("pmu: %s failed: %d\n", "reset_controller_register", ret);
115 static void __init pmu_reset_init(struct pmu_data *pmu)
121 struct pmu_data *pmu;
146 struct pmu_data *pmu = pmu_dom->pmu;
149 void __iomem *pmu_base = pmu->pmu_base;
150 void __iomem *pmc_base = pmu->pmc_base;
152 spin_lock_irqsave(&pmu->lock, flags);
172 spin_unlock_irqrestore(&pmu->lock, flags);
180 struct pmu_data *pmu = pmu_dom->pmu;
183 void __iomem *pmu_base = pmu->pmu_base;
184 void __iomem *pmc_base = pmu->pmc_base;
186 spin_lock_irqsave(&pmu->lock, flags);
206 spin_unlock_irqrestore(&pmu->lock, flags);
214 unsigned int val = readl_relaxed(domain->pmu->pmu_base + PMU_PWR);
228 struct pmu_data *pmu = irq_desc_get_handler_data(desc);
229 struct irq_chip_generic *gc = pmu->irq_gc;
230 struct irq_domain *domain = pmu->irq_domain;
266 static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq)
274 writel(0, pmu->pmc_base + PMC_IRQ_MASK);
275 writel(0, pmu->pmc_base + PMC_IRQ_CAUSE);
277 domain = irq_domain_add_linear(pmu->of_node, NR_PMU_IRQS,
295 gc->reg_base = pmu->pmc_base;
300 pmu->irq_domain = domain;
301 pmu->irq_gc = gc;
303 irq_set_handler_data(irq, pmu);
312 struct pmu_data *pmu;
315 pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
316 if (!pmu)
319 spin_lock_init(&pmu->lock);
320 pmu->pmc_base = initdata->pmc_base;
321 pmu->pmu_base = initdata->pmu_base;
323 pmu_reset_init(pmu);
330 domain->pmu = pmu;
340 ret = dove_init_pmu_irq(pmu, initdata->irq);
344 if (pmu->irq_domain)
345 irq_domain_associate_many(pmu->irq_domain,
353 * pmu: power-manager@d0000 {
354 * compatible = "marvell,dove-pmu";
363 * resets = <&pmu 16>;
369 * resets = <&pmu 18>;
376 struct pmu_data *pmu;
380 np_pmu = of_find_compatible_node(NULL, NULL, "marvell,dove-pmu");
390 pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
391 if (!pmu)
394 spin_lock_init(&pmu->lock);
395 pmu->of_node = np_pmu;
396 pmu->pmc_base = of_iomap(pmu->of_node, 0);
397 pmu->pmu_base = of_iomap(pmu->of_node, 1);
398 if (!pmu->pmc_base || !pmu->pmu_base) {
400 iounmap(pmu->pmu_base);
401 iounmap(pmu->pmc_base);
402 kfree(pmu);
406 pmu_reset_init(pmu);
416 domain->pmu = pmu;
436 if (args.np == pmu->of_node)
445 parent_irq = irq_of_parse_and_map(pmu->of_node, 0);
449 ret = dove_init_pmu_irq(pmu, parent_irq);