Lines Matching refs:ufshcd_writel
689 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
691 ufshcd_writel(hba, ~(1 << pos),
703 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
705 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
813 ufshcd_writel(hba, INT_AGGR_ENABLE |
827 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
839 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
850 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
852 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
867 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
1970 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
2099 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2100 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2101 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2106 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2269 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2291 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
4027 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4293 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4295 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4297 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4299 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4338 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
6199 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
6276 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
9189 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
9191 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);