Lines Matching refs:set
249 static int ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set);
844 * When run-stop registers are set to 1, it indicates the
911 * ufshcd_set_clk_freq - set UFS controller clock frequencies
913 * @scale_up: If True, set max possible frequency othewise set low frequency
935 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
953 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1364 * there's no initial frequency set. And it always requests to set
1585 * Also, exit from hibern8 mode and set the link as active.
2151 * @completion: initialize the completion only if this is set to true
2259 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2263 rw = set & INTERRUPT_MASK_RW_VER_10;
2264 set = rw | ((set ^ intrs) & intrs);
2266 set |= intrs;
2269 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2279 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2283 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2285 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2288 set &= ~intrs;
2291 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
3667 * @attr_set: attribute set type as uic command argument2
3678 "dme-set",
3679 "dme-peer-set"
3681 const char *set = action[!!peer];
3696 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3701 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
4353 * sequence kicks off. When controller is ready it will set
4375 * To initialize a UFS host controller HCE bit must be set to 1.
4380 * So without this delay the value HCE = 1, set in the previous
4601 * ufshcd_set_queue_depth - set lun queue depth
4605 * queueing. For WLUN, queue depth is set to 1. For best-effort
4606 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4709 /* DBD field should be set to 1 in mode sense(10) */
4731 * @depth: required depth to set
5051 * bit is not set.
5347 static int ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set)
5352 if (set)
5930 * ufshcd_update_uic_error - check and set fatal UIC error flags.
6985 "%s: Regulator capability was not set, actvIccLevel=%d",
7443 /* set 1ms timeout for PA_TACTIVATE */
7755 * and for removable UFS card as well, hence always set the parameter.
7757 * bActiveICCLevel as well so it is always safe to set this here.
7862 * enabled or set as high power mode.
7869 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
7915 "%s: %s set voltage failed, err=%d\n",
8132 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
8141 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
8284 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
8287 * @pwr_mode: device power mode to set
8289 * Returns 0 if requested power mode is set successfully
8290 * Returns non-zero if failed to set the requested power mode
8336 * callbacks hence set the RQF_PM flag so that it doesn't resume the
8725 * set the link state as active
9135 dev_err(hba->dev, "set dma mask failed\n");