Lines Matching defs:intr_status
4932 * @intr_status: interrupt status generated by the controller
4938 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
4942 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
4953 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
6138 * @intr_status: contains interrupts generated by the controller
6144 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
6148 hba->errors = UFSHCD_ERROR_MASK & intr_status;
6150 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
6151 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
6156 if (intr_status & UFSHCD_UIC_MASK)
6157 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
6159 if (intr_status & UTP_TASK_REQ_COMPL)
6162 if (intr_status & UTP_TRANSFER_REQ_COMPL)
6179 u32 intr_status, enabled_intr_status = 0;
6185 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6186 hba->ufs_stats.last_intr_status = intr_status;
6195 while (intr_status && retries--) {
6197 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
6198 if (intr_status)
6199 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
6203 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6210 intr_status,