Lines Matching defs:host
42 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
107 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
109 if (!host->is_lane_clks_enabled)
112 clk_disable_unprepare(host->tx_l1_sync_clk);
113 clk_disable_unprepare(host->tx_l0_sync_clk);
114 clk_disable_unprepare(host->rx_l1_sync_clk);
115 clk_disable_unprepare(host->rx_l0_sync_clk);
117 host->is_lane_clks_enabled = false;
120 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
123 struct device *dev = host->hba->dev;
125 if (host->is_lane_clks_enabled)
129 host->rx_l0_sync_clk);
134 host->tx_l0_sync_clk);
139 host->rx_l1_sync_clk);
144 host->tx_l1_sync_clk);
148 host->is_lane_clks_enabled = true;
152 clk_disable_unprepare(host->rx_l1_sync_clk);
154 clk_disable_unprepare(host->tx_l0_sync_clk);
156 clk_disable_unprepare(host->rx_l0_sync_clk);
161 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
164 struct device *dev = host->hba->dev;
170 &host->rx_l0_sync_clk, false);
175 &host->tx_l0_sync_clk, false);
180 if (host->hba->lanes_per_direction > 1) {
182 &host->rx_l1_sync_clk, false);
187 &host->tx_l1_sync_clk, true);
240 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
242 ufshcd_rmwl(host->hba, QUNIPRO_SEL,
243 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
250 * ufs_qcom_host_reset - reset host controller and PHY
255 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
258 if (!host->core_reset) {
267 ret = reset_control_assert(host->core_reset);
281 ret = reset_control_deassert(host->core_reset);
299 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
300 struct phy *phy = host->generic_phy;
308 dev_warn(hba->dev, "%s: host reset returned %d\n",
330 ufs_qcom_select_unipro_mode(host);
361 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
372 err = ufs_qcom_enable_lane_clks(host);
378 ufs_qcom_ice_enable(host);
395 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
428 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
455 if (ufs_qcom_cap_qunipro(host))
539 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
551 if (ufs_qcom_cap_qunipro(host))
560 * Some UFS devices (and may be host) have issues if LCC is
562 * before link startup which will make sure that both host
583 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
584 struct phy *phy = host->generic_phy;
592 ufs_qcom_disable_lane_clks(host);
596 ufs_qcom_disable_lane_clks(host);
604 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
605 struct phy *phy = host->generic_phy;
616 err = ufs_qcom_enable_lane_clks(host);
621 err = ufs_qcom_enable_lane_clks(host);
626 return ufs_qcom_ice_resume(host);
629 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
631 if (host->dev_ref_clk_ctrl_mmio &&
632 (enable ^ host->is_dev_ref_clk_enabled)) {
633 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
636 temp |= host->dev_ref_clk_en_mask;
638 temp &= ~host->dev_ref_clk_en_mask;
649 gating_wait = host->hba->dev_info.clk_gating_wait_us;
665 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
671 readl(host->dev_ref_clk_ctrl_mmio);
681 host->is_dev_ref_clk_enabled = enable;
690 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
716 if (host->hw_ver.major == 0x1) {
719 * UFS host controller hardware even though capability
742 ufs_qcom_dev_ref_clk_ctrl(host, true);
744 if (host->hw_ver.major >= 0x4) {
773 memcpy(&host->dev_req_params,
779 ufs_qcom_dev_ref_clk_ctrl(host, false);
822 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
824 if (host->hw_ver.major == 0x1)
832 * @hba: host controller instance
834 * QCOM UFS host controller might have some non standard behaviours (quirks)
836 * quirks to standard UFS host controller driver so standard takes them into
841 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
843 if (host->hw_ver.major == 0x01) {
848 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
854 if (host->hw_ver.major == 0x2) {
857 if (!ufs_qcom_cap_qunipro(host))
867 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
875 if (host->hw_ver.major >= 0x2) {
876 host->caps = UFS_QCOM_CAP_QUNIPRO |
883 * @hba: host controller instance
892 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
900 if (!host)
908 ufs_qcom_dev_ref_clk_ctrl(host, false);
916 ufs_qcom_dev_ref_clk_ctrl(host, true);
927 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
931 ufs_qcom_assert_reset(host->hba);
940 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
944 ufs_qcom_deassert_reset(host->hba);
973 * @hba: host controller instance
986 struct ufs_qcom_host *host;
992 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
993 if (!host) {
995 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
999 /* Make a two way bind between the qcom host and the hba */
1000 host->hba = hba;
1001 ufshcd_set_variant(hba, host);
1004 host->core_reset = devm_reset_control_get(hba->dev, "rst");
1005 if (IS_ERR(host->core_reset)) {
1006 err = PTR_ERR(host->core_reset);
1008 host->core_reset = NULL;
1013 host->rcdev.of_node = dev->of_node;
1014 host->rcdev.ops = &ufs_qcom_reset_ops;
1015 host->rcdev.owner = dev->driver->owner;
1016 host->rcdev.nr_resets = 1;
1017 err = devm_reset_controller_register(dev, &host->rcdev);
1028 host->generic_phy = devm_phy_get(dev, "ufsphy");
1030 if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1039 } else if (IS_ERR(host->generic_phy)) {
1041 host->generic_phy = NULL;
1043 err = PTR_ERR(host->generic_phy);
1049 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1051 if (IS_ERR(host->device_reset)) {
1052 err = PTR_ERR(host->device_reset);
1058 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1059 &host->hw_ver.minor, &host->hw_ver.step);
1065 if (host->hw_ver.major >= 0x02) {
1066 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1067 host->dev_ref_clk_en_mask = BIT(26);
1073 host->dev_ref_clk_ctrl_mmio =
1075 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1079 PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1080 host->dev_ref_clk_ctrl_mmio = NULL;
1082 host->dev_ref_clk_en_mask = BIT(5);
1086 err = ufs_qcom_init_lane_clks(host);
1093 err = ufs_qcom_ice_init(host);
1100 ufs_qcom_hosts[hba->dev->id] = host;
1102 host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1103 ufs_qcom_get_default_testbus_cfg(host);
1104 err = ufs_qcom_testbus_config(host);
1121 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1123 ufs_qcom_disable_lane_clks(host);
1124 phy_power_off(host->generic_phy);
1125 phy_exit(host->generic_phy);
1164 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1166 if (!ufs_qcom_cap_qunipro(host))
1175 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1179 if (!ufs_qcom_cap_qunipro(host))
1200 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1202 if (!ufs_qcom_cap_qunipro(host))
1212 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1213 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1246 struct ufs_qcom_host *host;
1257 host = ufshcd_get_variant(hba);
1258 if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1261 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1268 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1271 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1274 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1280 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1283 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1286 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1289 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1292 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1295 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1298 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1302 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1304 if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1305 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1307 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1309 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1310 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1314 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1317 host->testbus.select_major = TSTBUS_UNIPRO;
1318 host->testbus.select_minor = 37;
1321 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1323 if (host->testbus.select_major >= TSTBUS_MAX) {
1324 dev_err(host->hba->dev,
1326 __func__, host->testbus.select_major);
1333 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1339 if (!host)
1342 if (!ufs_qcom_testbus_cfg_is_ok(host))
1345 switch (host->testbus.select_major) {
1402 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1403 (u32)host->testbus.select_major << 19,
1405 ufshcd_rmwl(host->hba, mask,
1406 (u32)host->testbus.select_minor << offset,
1408 ufs_qcom_enable_test_bus(host);
1434 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1437 if (!host->device_reset)
1444 gpiod_set_value_cansleep(host->device_reset, 1);
1447 gpiod_set_value_cansleep(host->device_reset, 0);