Lines Matching defs:host
61 #define qcom_ice_writel(host, val, reg) \
62 writel((val), (host)->ice_mmio + (reg))
63 #define qcom_ice_readl(host, reg) \
64 readl((host)->ice_mmio + (reg))
66 static bool qcom_ice_supported(struct ufs_qcom_host *host)
68 struct device *dev = host->hba->dev;
69 u32 regval = qcom_ice_readl(host, QCOM_ICE_REG_VERSION);
85 regval = qcom_ice_readl(host, QCOM_ICE_REG_FUSE_SETTING);
95 int ufs_qcom_ice_init(struct ufs_qcom_host *host)
97 struct ufs_hba *hba = host->hba;
118 host->ice_mmio = devm_ioremap_resource(dev, res);
119 if (IS_ERR(host->ice_mmio)) {
120 err = PTR_ERR(host->ice_mmio);
125 if (!qcom_ice_supported(host))
136 static void qcom_ice_low_power_mode_enable(struct ufs_qcom_host *host)
140 regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL);
146 qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
149 static void qcom_ice_optimization_enable(struct ufs_qcom_host *host)
154 regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL);
158 qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
162 int ufs_qcom_ice_enable(struct ufs_qcom_host *host)
164 if (!(host->hba->caps & UFSHCD_CAP_CRYPTO))
166 qcom_ice_low_power_mode_enable(host);
167 qcom_ice_optimization_enable(host);
168 return ufs_qcom_ice_resume(host);
172 static int qcom_ice_wait_bist_status(struct ufs_qcom_host *host)
178 reg = qcom_ice_readl(host, QCOM_ICE_REG_BIST_STATUS);
188 int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
192 if (!(host->hba->caps & UFSHCD_CAP_CRYPTO))
195 err = qcom_ice_wait_bist_status(host);
197 dev_err(host->hba->dev, "BIST status error (%d)\n", err);