Lines Matching refs:hba
63 static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba)
65 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
70 static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
75 ufshcd_dme_get(hba,
81 ufshcd_dme_set(hba,
84 ufshcd_dme_get(hba,
87 ufshcd_dme_set(hba,
90 ufshcd_dme_get(hba,
95 ufshcd_dme_set(hba,
98 ufshcd_dme_get(hba,
101 ufshcd_dme_set(hba,
106 static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
112 dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n",
114 hba->caps &= ~UFSHCD_CAP_CRYPTO;
118 static void ufs_mtk_host_reset(struct ufs_hba *hba)
120 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
133 static void ufs_mtk_init_reset_control(struct ufs_hba *hba,
137 *rc = devm_reset_control_get(hba->dev, str);
139 dev_info(hba->dev, "Failed to get reset control %s: %ld\n",
145 static void ufs_mtk_init_reset(struct ufs_hba *hba)
147 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
149 ufs_mtk_init_reset_control(hba, &host->hci_reset,
151 ufs_mtk_init_reset_control(hba, &host->unipro_reset,
153 ufs_mtk_init_reset_control(hba, &host->crypto_reset,
157 static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
160 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
164 hba->vps->hba_enable_delay_us = 0;
166 hba->vps->hba_enable_delay_us = 600;
167 ufs_mtk_host_reset(hba);
170 if (hba->caps & UFSHCD_CAP_CRYPTO)
171 ufs_mtk_crypto_enable(hba);
177 static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
179 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
180 struct device *dev = hba->dev;
215 static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
217 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
228 ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL);
230 ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
237 value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
246 dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
262 static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba,
265 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
267 if (hba->dev_info.clk_gating_wait_us) {
269 hba->dev_info.clk_gating_wait_us;
277 static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
286 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
287 val = ufshcd_readl(hba, REG_UFS_PROBE);
303 static void ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on)
305 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
335 static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
337 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
342 if (!ufs_mtk_is_boost_crypt_enabled(hba))
351 dev_info(hba->dev, "clk_prepare_enable(): %d\n",
359 dev_info(hba->dev,
367 dev_info(hba->dev,
376 dev_info(hba->dev,
383 dev_info(hba->dev,
391 static int ufs_mtk_init_host_clk(struct ufs_hba *hba, const char *name,
396 ret = ufs_mtk_get_host_clk(hba->dev, name, clk);
398 dev_info(hba->dev, "%s: failed to get %s: %d", __func__,
405 static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
407 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
409 struct device *dev = hba->dev;
415 if (!ufs_mtk_is_boost_crypt_enabled(hba))
437 if (ufs_mtk_init_host_clk(hba, "crypt_mux",
441 if (ufs_mtk_init_host_clk(hba, "crypt_lp",
445 if (ufs_mtk_init_host_clk(hba, "crypt_perf",
460 * @hba: host controller instance
466 static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
469 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
482 if (ufshcd_is_link_off(hba)) {
484 } else if (ufshcd_is_link_hibern8(hba) ||
485 (!ufshcd_can_hibern8_during_gating(hba) &&
486 ufshcd_is_auto_hibern8_enabled(hba))) {
492 ret = ufs_mtk_wait_link_state(hba,
500 ufs_mtk_boost_crypt(hba, on);
501 ufs_mtk_setup_ref_clk(hba, on);
502 ufs_mtk_mphy_power_on(hba, on);
505 ufs_mtk_mphy_power_on(hba, on);
506 ufs_mtk_setup_ref_clk(hba, on);
507 ufs_mtk_boost_crypt(hba, on);
515 * @hba: host controller instance
523 static int ufs_mtk_init(struct ufs_hba *hba)
526 struct device *dev = hba->dev;
537 host->hba = hba;
538 ufshcd_set_variant(hba, host);
549 ufs_mtk_init_host_caps(hba);
552 err = ufs_mtk_bind_mphy(hba);
556 ufs_mtk_init_reset(hba);
559 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
562 hba->caps |= UFSHCD_CAP_CLK_GATING;
565 hba->caps |= UFSHCD_CAP_CRYPTO;
568 hba->caps |= UFSHCD_CAP_WB_EN;
569 hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL;
570 hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80);
579 ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
584 ufshcd_set_variant(hba, NULL);
589 static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
621 static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba,
630 ret = ufs_mtk_pre_pwr_change(hba, dev_max_params,
643 static int ufs_mtk_unipro_set_pm(struct ufs_hba *hba, bool lpm)
646 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
648 ret = ufshcd_dme_set(hba,
663 static int ufs_mtk_pre_link(struct ufs_hba *hba)
668 ret = ufs_mtk_unipro_set_pm(hba, false);
677 ret = ufshcd_disable_host_tx_lcc(hba);
682 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
688 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
693 static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
698 if (ufshcd_is_clkgating_allowed(hba)) {
699 if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit)
701 hba->ahit);
704 spin_lock_irqsave(hba->host->host_lock, flags);
705 hba->clk_gating.delay_ms = ah_ms + 5;
706 spin_unlock_irqrestore(hba->host->host_lock, flags);
710 static int ufs_mtk_post_link(struct ufs_hba *hba)
713 ufs_mtk_cfg_unipro_cg(hba, true);
716 if (ufshcd_is_auto_hibern8_supported(hba)) {
717 ufshcd_auto_hibern8_update(hba,
722 ufs_mtk_setup_clk_gating(hba);
727 static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
734 ret = ufs_mtk_pre_link(hba);
737 ret = ufs_mtk_post_link(hba);
747 static int ufs_mtk_device_reset(struct ufs_hba *hba)
767 dev_info(hba->dev, "device reset done\n");
772 static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
776 err = ufshcd_hba_enable(hba);
780 err = ufs_mtk_unipro_set_pm(hba, false);
784 err = ufshcd_uic_hibern8_exit(hba);
786 ufshcd_set_link_active(hba);
790 err = ufshcd_make_hba_operational(hba);
797 static int ufs_mtk_link_set_lpm(struct ufs_hba *hba)
801 err = ufs_mtk_unipro_set_pm(hba, true);
804 ufs_mtk_unipro_set_pm(hba, false);
811 static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hba, bool lpm)
813 if (!hba->vreg_info.vccq2 || !hba->vreg_info.vcc)
816 if (lpm && !hba->vreg_info.vcc->enabled)
817 regulator_set_mode(hba->vreg_info.vccq2->reg,
820 regulator_set_mode(hba->vreg_info.vccq2->reg,
824 static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
829 if (ufshcd_is_link_hibern8(hba)) {
830 err = ufs_mtk_link_set_lpm(hba);
837 ufshcd_set_link_off(hba);
845 ufs_mtk_vreg_set_lpm(hba, true);
848 if (ufshcd_is_link_off(hba))
854 static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
858 if (ufshcd_is_link_hibern8(hba)) {
859 ufs_mtk_vreg_set_lpm(hba, false);
860 err = ufs_mtk_link_set_hpm(hba);
862 err = ufshcd_link_recovery(hba);
870 static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba)
872 ufshcd_dump_regs(hba, REG_UFS_REFCLK_CTRL, 0x4, "Ref-Clk Ctrl ");
874 ufshcd_dump_regs(hba, REG_UFS_EXTREG, 0x4, "Ext Reg ");
876 ufshcd_dump_regs(hba, REG_UFS_MPHYCTRL,
881 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
882 ufshcd_dump_regs(hba, REG_UFS_PROBE, 0x4, "Debug Probe ");
885 static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
887 struct ufs_dev_info *dev_info = &hba->dev_info;
891 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
899 ufs_mtk_setup_ref_clk_wait_us(hba, 1, 1);
901 ufs_mtk_setup_ref_clk_wait_us(hba, 30, 30);
903 ufs_mtk_setup_ref_clk_wait_us(hba, 100, 32);
908 static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
910 ufshcd_fixup_dev_quirks(hba, ufs_mtk_dev_fixups);
961 struct ufs_hba *hba = platform_get_drvdata(pdev);
964 ufshcd_remove(hba);