Lines Matching refs:ufs
23 #include "ufs-exynos.h"
110 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en);
111 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en);
113 static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs)
115 exynos_ufs_auto_ctrl_hcc(ufs, true);
118 static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs)
120 exynos_ufs_auto_ctrl_hcc(ufs, false);
124 struct exynos_ufs *ufs, u32 *val)
126 *val = hci_readl(ufs, HCI_MISC);
127 exynos_ufs_auto_ctrl_hcc(ufs, false);
131 struct exynos_ufs *ufs, u32 *val)
133 hci_writel(ufs, *val, HCI_MISC);
136 static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs)
138 exynos_ufs_ctrl_clkstop(ufs, true);
141 static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs)
143 exynos_ufs_ctrl_clkstop(ufs, false);
146 static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
151 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
153 struct ufs_hba *hba = ufs->hba;
154 u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
158 for_each_ufs_tx_lane(ufs, i)
160 for_each_ufs_rx_lane(ufs, i) {
166 for_each_ufs_tx_lane(ufs, i)
181 static int exynos7_ufs_post_link(struct exynos_ufs *ufs)
183 struct ufs_hba *hba = ufs->hba;
187 for_each_ufs_tx_lane(ufs, i) {
191 TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000)));
202 static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs,
205 unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE);
210 static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs,
213 struct ufs_hba *hba = ufs->hba;
233 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en)
235 u32 misc = hci_readl(ufs, HCI_MISC);
238 hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC);
240 hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC);
243 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en)
245 u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL);
246 u32 misc = hci_readl(ufs, HCI_MISC);
249 hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC);
250 hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
252 hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
253 hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC);
257 static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs)
259 struct ufs_hba *hba = ufs->hba;
273 ufs->clk_hci_core = clki->clk;
275 ufs->clk_unipro_main = clki->clk;
279 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) {
285 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main);
286 pclk_rate = clk_get_rate(ufs->clk_hci_core);
287 f_min = ufs->pclk_avail_min;
288 f_max = ufs->pclk_avail_max;
290 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
306 ufs->pclk_rate = pclk_rate;
307 ufs->pclk_div = div;
313 static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs)
315 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
318 val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL);
319 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div),
324 static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs)
326 struct ufs_hba *hba = ufs->hba;
327 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
333 static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs)
335 struct ufs_hba *hba = ufs->hba;
336 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
344 clk_period = UNIPRO_PCLK_PERIOD(ufs);
364 long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period)
367 long pclk_rate = ufs->pclk_rate;
370 clk_period = UNIPRO_PCLK_PERIOD(ufs);
376 static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs)
378 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
379 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
382 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec);
384 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec);
386 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec);
388 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec);
390 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec);
392 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt);
395 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec);
397 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec);
399 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec);
401 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec);
403 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt);
405 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt);
408 static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs)
410 struct ufs_hba *hba = ufs->hba;
411 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
414 exynos_ufs_set_pwm_clk_div(ufs);
418 for_each_ufs_rx_lane(ufs, i) {
420 ufs->drv_data->uic_attr->rx_filler_enable);
437 for_each_ufs_tx_lane(ufs, i) {
456 ufs->drv_data->uic_attr->tx_min_activatetime);
462 static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs)
464 struct ufs_hba *hba = ufs->hba;
465 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
470 for_each_ufs_rx_lane(ufs, i) {
492 for_each_ufs_rx_lane(ufs, i) {
507 for_each_ufs_rx_lane(ufs, i) {
531 static void exynos_ufs_establish_connt(struct exynos_ufs *ufs)
533 struct ufs_hba *hba = ufs->hba;
554 static void exynos_ufs_config_smu(struct exynos_ufs *ufs)
558 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
561 reg = ufsp_readl(ufs, UFSPRSECURITY);
562 ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY);
563 ufsp_writel(ufs, 0x0, UFSPSBEGIN0);
564 ufsp_writel(ufs, 0xffffffff, UFSPSEND0);
565 ufsp_writel(ufs, 0xff, UFSPSLUN0);
566 ufsp_writel(ufs, 0xf1, UFSPSCTRL0);
568 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
571 static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs,
574 struct ufs_hba *hba = ufs->hba;
593 mask = exynos_ufs_calc_time_cntr(ufs, sync_len);
598 for_each_ufs_rx_lane(ufs, i)
609 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
610 struct phy *generic_phy = ufs->phy;
642 if (ufs->drv_data->pre_pwr_change)
643 ufs->drv_data->pre_pwr_change(ufs, dev_req_params);
646 exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params);
671 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
672 struct phy *generic_phy = ufs->phy;
684 if (ufs->drv_data->post_pwr_change)
685 ufs->drv_data->post_pwr_change(ufs, pwr_req);
711 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
714 type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);
717 hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE);
719 hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE);
725 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
728 type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE);
733 hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE);
739 hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE);
744 static int exynos_ufs_phy_init(struct exynos_ufs *ufs)
746 struct ufs_hba *hba = ufs->hba;
747 struct phy *generic_phy = ufs->phy;
750 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) {
752 &ufs->avail_ln_rx);
754 &ufs->avail_ln_tx);
755 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx,
757 ufs->avail_ln_rx, ufs->avail_ln_tx);
760 phy_set_bus_width(generic_phy, ufs->avail_ln_rx);
776 static void exynos_ufs_config_unipro(struct exynos_ufs *ufs)
778 struct ufs_hba *hba = ufs->hba;
781 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
783 ufs->drv_data->uic_attr->tx_trailingclks);
785 ufs->drv_data->uic_attr->pa_dbg_option_suite);
788 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
792 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER);
795 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER);
798 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER);
801 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER);
804 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER);
811 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
814 exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2);
815 exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3);
816 exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4);
817 exynos_ufs_set_unipro_pclk_div(ufs);
820 exynos_ufs_config_unipro(ufs);
823 exynos_ufs_phy_init(ufs);
824 exynos_ufs_config_phy_time_attr(ufs);
825 exynos_ufs_config_phy_cap_attr(ufs);
827 if (ufs->drv_data->pre_link)
828 ufs->drv_data->pre_link(ufs);
833 static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs)
837 val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL);
838 hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL);
843 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
844 struct phy *generic_phy = ufs->phy;
845 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
847 exynos_ufs_establish_connt(ufs);
848 exynos_ufs_fit_aggr_timeout(ufs);
850 hci_writel(ufs, 0xa, HCI_DATA_REORDER);
851 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_TXPRDT_ENTRY_SIZE);
852 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_RXPRDT_ENTRY_SIZE);
853 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE);
854 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE);
855 hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN);
857 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)
871 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER))
876 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
900 if (ufs->drv_data->post_link)
901 ufs->drv_data->post_link(ufs);
906 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
915 ufs->drv_data = drv_data;
921 if (ufs->drv_data && ufs->drv_data->uic_attr) {
922 attr = ufs->drv_data->uic_attr;
929 ufs->pclk_avail_min = PCLK_AVAIL_MIN;
930 ufs->pclk_avail_max = PCLK_AVAIL_MAX;
947 struct exynos_ufs *ufs;
950 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
951 if (!ufs)
955 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
956 if (IS_ERR(ufs->reg_hci)) {
958 return PTR_ERR(ufs->reg_hci);
962 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro");
963 if (IS_ERR(ufs->reg_unipro)) {
965 return PTR_ERR(ufs->reg_unipro);
968 /* ufs protector */
969 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp");
970 if (IS_ERR(ufs->reg_ufsp)) {
971 dev_err(dev, "cannot ioremap for ufs protector register\n");
972 return PTR_ERR(ufs->reg_ufsp);
975 ret = exynos_ufs_parse_dt(dev, ufs);
981 ufs->phy = devm_phy_get(dev, "ufs-phy");
982 if (IS_ERR(ufs->phy)) {
983 ret = PTR_ERR(ufs->phy);
984 dev_err(dev, "failed to get ufs-phy\n");
988 ret = phy_power_on(ufs->phy);
992 ufs->hba = hba;
993 ufs->opts = ufs->drv_data->opts;
994 ufs->rx_sel_idx = PA_MAXDATALANES;
995 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX)
996 ufs->rx_sel_idx = 0;
997 hba->priv = (void *)ufs;
998 hba->quirks = ufs->drv_data->quirks;
999 if (ufs->drv_data->drv_init) {
1000 ret = ufs->drv_data->drv_init(dev, ufs);
1007 ret = exynos_ufs_get_clk_info(ufs);
1010 exynos_ufs_specify_phy_time_attr(ufs);
1011 exynos_ufs_config_smu(ufs);
1015 phy_power_off(ufs->phy);
1023 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1028 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
1030 hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST);
1033 if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK))
1041 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
1047 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1049 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT);
1051 hci_writel(ufs, 1 << 0, HCI_GPIO_OUT);
1056 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1057 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1060 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1061 exynos_ufs_disable_auto_ctrl_hcc(ufs);
1062 exynos_ufs_ungate_clks(ufs);
1064 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
1075 ufs->entry_hibern8_t);
1089 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1095 if (ufshcd_is_hs_mode(&ufs->dev_req_params))
1108 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB))
1109 exynos_ufs_establish_connt(ufs);
1111 ufs->entry_hibern8_t = ktime_get();
1112 exynos_ufs_gate_clks(ufs);
1113 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1114 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1121 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1132 exynos_ufs_calc_pwm_clk_div(ufs);
1133 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL))
1134 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1194 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1197 phy_power_off(ufs->phy);
1204 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1207 phy_power_on(ufs->phy);
1209 exynos_ufs_config_smu(ufs);
1250 .compatible = "samsung,exynos7-ufs",
1273 { .compatible = "samsung,exynos7-ufs",