Lines Matching refs:val
176 u8 bursts, val;
180 val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
181 if (val != 0xff)
182 bursts &= val;
184 val = of_getintprop_default(dma_dp->parent, "burst-sizes", 0xff);
185 if (val != 0xff)
186 bursts &= val;
204 static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
206 sbus_writeb(val, esp->regs + (reg * 4UL));
226 u32 val;
239 val = dma_read32(DMA_CSR);
240 dma_write32(val | DMA_RST_SCSI, DMA_CSR);
241 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
283 val = dma_read32(DMA_CSR);
284 dma_write32(val | DMA_3CLKS, DMA_CSR);
289 val = dma_read32(DMA_CSR);
290 val &= ~DMA_3CLKS;
291 val |= DMA_2CLKS;
293 val &= ~DMA_BRST_SZ;
294 val |= DMA_BRST32;
296 dma_write32(val, DMA_CSR);
300 val = dma_read32(DMA_CSR);
301 val |= DMA_ADD_ENABLE;
302 val &= ~DMA_BCNT_ENAB;
304 val |= DMA_ESC_BURST;
306 val &= ~(DMA_ESC_BURST);
308 dma_write32(val, DMA_CSR);
316 val = dma_read32(DMA_CSR);
317 dma_write32(val | DMA_INT_ENAB, DMA_CSR);
364 u32 val;
368 while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
377 val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
378 val |= DMA_FIFO_INV;
379 dma_write32(val, DMA_CSR);
380 val &= ~DMA_FIFO_INV;
381 dma_write32(val, DMA_CSR);
498 u32 val = dma_read32(DMA_CSR);
500 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
558 u32 val;
563 val = dma_read32(DMA_CSR);
564 dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);