Lines Matching refs:DMA_CSR
57 switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
216 if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
239 val = dma_read32(DMA_CSR);
240 dma_write32(val | DMA_RST_SCSI, DMA_CSR);
241 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
245 dma_write32(DMA_RESET_FAS366, DMA_CSR);
246 dma_write32(DMA_RST_SCSI, DMA_CSR);
265 while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
275 dma_write32(0, DMA_CSR);
276 dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
283 val = dma_read32(DMA_CSR);
284 dma_write32(val | DMA_3CLKS, DMA_CSR);
289 val = dma_read32(DMA_CSR);
296 dma_write32(val, DMA_CSR);
300 val = dma_read32(DMA_CSR);
308 dma_write32(val, DMA_CSR);
316 val = dma_read32(DMA_CSR);
317 dma_write32(val | DMA_INT_ENAB, DMA_CSR);
328 csr = dma_read32(DMA_CSR);
333 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
336 while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
349 dma_write32(DMA_RST_SCSI, DMA_CSR);
356 dma_write32(0, DMA_CSR);
357 dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
368 while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
379 dma_write32(val, DMA_CSR);
381 dma_write32(val, DMA_CSR);
410 dma_write32(csr, DMA_CSR);
412 csr = dma_read32(DMA_CSR);
418 dma_write32(csr, DMA_CSR);
432 u32 csr = dma_read32(DMA_CSR);
498 u32 val = dma_read32(DMA_CSR);
500 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
563 val = dma_read32(DMA_CSR);
564 dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);