Lines Matching refs:DMA_CSR
23 #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
66 if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
75 val = dma_read32(DMA_CSR);
76 dma_write32(val | DMA_RST_SCSI, DMA_CSR);
77 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
80 val = dma_read32(DMA_CSR);
81 dma_write32(val | DMA_INT_ENAB, DMA_CSR);
89 csr = dma_read32(DMA_CSR);
93 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
96 while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
112 while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
123 dma_write32(val, DMA_CSR);
125 dma_write32(val, DMA_CSR);
137 csr = dma_read32(DMA_CSR);
143 dma_write32(csr, DMA_CSR);
151 u32 csr = dma_read32(DMA_CSR);
255 val = dma_read32(DMA_CSR);
256 dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);