Lines Matching defs:ctrl_info
81 static int sis_wait_for_ctrl_ready_with_timeout(struct pqi_ctrl_info *ctrl_info,
90 status = readl(&ctrl_info->registers->sis_firmware_status);
93 dev_err(&ctrl_info->pci_dev->dev,
96 &ctrl_info->registers->sis_mailbox[7]));
103 dev_err(&ctrl_info->pci_dev->dev,
114 int sis_wait_for_ctrl_ready(struct pqi_ctrl_info *ctrl_info)
116 return sis_wait_for_ctrl_ready_with_timeout(ctrl_info,
120 int sis_wait_for_ctrl_ready_resume(struct pqi_ctrl_info *ctrl_info)
122 return sis_wait_for_ctrl_ready_with_timeout(ctrl_info,
126 bool sis_is_firmware_running(struct pqi_ctrl_info *ctrl_info)
131 status = readl(&ctrl_info->registers->sis_firmware_status);
139 dev_err(&ctrl_info->pci_dev->dev,
141 readl(&ctrl_info->registers->sis_mailbox[7]));
146 bool sis_is_kernel_up(struct pqi_ctrl_info *ctrl_info)
148 return readl(&ctrl_info->registers->sis_firmware_status) &
157 static int sis_send_sync_cmd(struct pqi_ctrl_info *ctrl_info,
166 registers = ctrl_info->registers;
212 dev_err(&ctrl_info->pci_dev->dev,
233 int sis_get_ctrl_properties(struct pqi_ctrl_info *ctrl_info)
242 rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_ADAPTER_PROPERTIES,
259 ctrl_info->pqi_reset_quiesce_supported = true;
264 int sis_get_pqi_capabilities(struct pqi_ctrl_info *ctrl_info)
271 rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_PQI_CAPABILITIES,
276 ctrl_info->max_sg_entries = params.mailbox[1];
277 ctrl_info->max_transfer_size = params.mailbox[2];
278 ctrl_info->max_outstanding_requests = params.mailbox[3];
279 ctrl_info->config_table_offset = params.mailbox[4];
280 ctrl_info->config_table_length = params.mailbox[5];
285 int sis_init_base_struct_addr(struct pqi_ctrl_info *ctrl_info)
301 error_buffer_paddr = (unsigned long)ctrl_info->error_buffer_dma_handle;
310 put_unaligned_le32(ctrl_info->max_io_slots,
313 bus_address = dma_map_single(&ctrl_info->pci_dev->dev, base_struct,
315 if (dma_mapping_error(&ctrl_info->pci_dev->dev, bus_address)) {
325 rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_INIT_BASE_STRUCT_ADDRESS,
328 dma_unmap_single(&ctrl_info->pci_dev->dev, bus_address,
339 struct pqi_ctrl_info *ctrl_info, u32 bit)
349 readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
352 if (readl(&ctrl_info->registers->sis_firmware_status) &
358 dev_err(&ctrl_info->pci_dev->dev,
370 static inline int sis_set_doorbell_bit(struct pqi_ctrl_info *ctrl_info, u32 bit)
372 writel(bit, &ctrl_info->registers->sis_host_to_ctrl_doorbell);
374 return sis_wait_for_doorbell_bit_to_clear(ctrl_info, bit);
377 void sis_enable_msix(struct pqi_ctrl_info *ctrl_info)
379 sis_set_doorbell_bit(ctrl_info, SIS_ENABLE_MSIX);
382 void sis_enable_intx(struct pqi_ctrl_info *ctrl_info)
384 sis_set_doorbell_bit(ctrl_info, SIS_ENABLE_INTX);
387 void sis_shutdown_ctrl(struct pqi_ctrl_info *ctrl_info)
389 if (readl(&ctrl_info->registers->sis_firmware_status) &
394 &ctrl_info->registers->sis_host_to_ctrl_doorbell);
397 int sis_pqi_reset_quiesce(struct pqi_ctrl_info *ctrl_info)
399 return sis_set_doorbell_bit(ctrl_info, SIS_PQI_RESET_QUIESCE);
402 int sis_reenable_sis_mode(struct pqi_ctrl_info *ctrl_info)
404 return sis_set_doorbell_bit(ctrl_info, SIS_REENABLE_SIS_MODE);
407 void sis_write_driver_scratch(struct pqi_ctrl_info *ctrl_info, u32 value)
409 writel(value, &ctrl_info->registers->sis_driver_scratch);
412 u32 sis_read_driver_scratch(struct pqi_ctrl_info *ctrl_info)
414 return readl(&ctrl_info->registers->sis_driver_scratch);
417 void sis_soft_reset(struct pqi_ctrl_info *ctrl_info)
420 &ctrl_info->registers->sis_host_to_ctrl_doorbell);