Lines Matching refs:ctrl_status
308 reg_val = readw(&ha->reg->ctrl_status);
4679 uint32_t ctrl_status;
4693 ctrl_status = readw(&ha->reg->ctrl_status);
4694 if ((ctrl_status & CSR_SCSI_RESET_INTR) != 0)
4695 writel(set_rmask(CSR_SCSI_RESET_INTR), &ha->reg->ctrl_status);
4698 writel(set_rmask(CSR_SOFT_RESET), &ha->reg->ctrl_status);
4699 readl(&ha->reg->ctrl_status);
4714 uint32_t ctrl_status;
4725 ctrl_status = readw(&ha->reg->ctrl_status);
4728 if ((ctrl_status & CSR_NET_RESET_INTR) == 0)
4734 if ((ctrl_status & CSR_NET_RESET_INTR) != 0) {
4740 writel(set_rmask(CSR_NET_RESET_INTR), &ha->reg->ctrl_status);
4741 readl(&ha->reg->ctrl_status);
4749 ctrl_status = readw(&ha->reg->ctrl_status);
4752 if ((ctrl_status & CSR_SOFT_RESET) == 0) {
4765 ctrl_status = readw(&ha->reg->ctrl_status);
4766 if ((ctrl_status & CSR_SCSI_RESET_INTR) != 0) {
4767 writel(set_rmask(CSR_SCSI_RESET_INTR), &ha->reg->ctrl_status);
4768 readl(&ha->reg->ctrl_status);
4781 writel(set_rmask(CSR_FORCE_SOFT_RESET), &ha->reg->ctrl_status);
4782 readl(&ha->reg->ctrl_status);
4788 ctrl_status = readw(&ha->reg->ctrl_status);
4791 if ((ctrl_status & CSR_FORCE_SOFT_RESET) == 0) {
5418 while ((readw(&ha->reg->ctrl_status) &
5495 &ha->reg->ctrl_status);
5496 readl(&ha->reg->ctrl_status);