Lines Matching defs:vha
9 #define ISPREG(vha) (&(vha)->hw->iobase->isp24)
11 #define IOBASE(vha) IOBAR(ISPREG(vha))
136 qla27xx_fwdt_entry_t0(struct scsi_qla_host *vha,
139 ql_dbg(ql_dbg_misc, vha, 0xd100,
147 qla27xx_fwdt_entry_t255(struct scsi_qla_host *vha,
150 ql_dbg(ql_dbg_misc, vha, 0xd1ff,
159 qla27xx_fwdt_entry_t256(struct scsi_qla_host *vha,
167 ql_dbg(ql_dbg_misc, vha, 0xd200,
169 qla27xx_read_window(ISPREG(vha), addr, offset, count, width, buf, len);
175 qla27xx_fwdt_entry_t257(struct scsi_qla_host *vha,
182 ql_dbg(ql_dbg_misc, vha, 0xd201,
184 qla27xx_write_reg(ISPREG(vha), IOBASE(vha), addr, buf);
185 qla27xx_write_reg(ISPREG(vha), offset, data, buf);
191 qla27xx_fwdt_entry_t258(struct scsi_qla_host *vha,
201 ql_dbg(ql_dbg_misc, vha, 0xd202,
203 qla27xx_write_reg(ISPREG(vha), banksel, bank, buf);
204 qla27xx_read_window(ISPREG(vha), addr, offset, count, width, buf, len);
210 qla27xx_fwdt_entry_t259(struct scsi_qla_host *vha,
219 ql_dbg(ql_dbg_misc, vha, 0xd203,
221 qla27xx_write_reg(ISPREG(vha), IOBASE(vha), addr, buf);
222 qla27xx_write_reg(ISPREG(vha), banksel, bank, buf);
223 qla27xx_write_reg(ISPREG(vha), offset, data, buf);
229 qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha,
234 ql_dbg(ql_dbg_misc, vha, 0xd204,
237 qla27xx_read_reg(ISPREG(vha), offset, buf, len);
243 qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha,
249 ql_dbg(ql_dbg_misc, vha, 0xd205,
251 qla27xx_write_reg(ISPREG(vha), offset, data, buf);
257 qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha,
266 ql_dbg(ql_dbg_misc, vha, 0xd206,
272 end = vha->hw->fw_memory_size;
276 start = vha->hw->fw_shared_ram_start;
277 end = vha->hw->fw_shared_ram_end;
283 start = vha->hw->fw_ddr_ram_start;
284 end = vha->hw->fw_ddr_ram_end;
295 ql_dbg(ql_dbg_misc, vha, 0xd022,
302 ql_dbg(ql_dbg_misc, vha, 0xd023,
312 rc = qla24xx_dump_ram(vha->hw, start, buf, dwords, &buf);
314 ql_dbg(ql_dbg_async, vha, 0xffff,
326 qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
334 ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd207,
337 for (i = 0; i < vha->hw->max_req_queues; i++) {
338 struct req_que *req = vha->hw->req_q_map[i];
351 for (i = 0; i < vha->hw->max_rsp_queues; i++) {
352 struct rsp_que *rsp = vha->hw->rsp_q_map[i];
366 struct qla_hw_data *ha = vha->hw;
377 ql_dbg(ql_dbg_misc, vha, 0xd026,
393 qla27xx_fwdt_entry_t264(struct scsi_qla_host *vha,
396 ql_dbg(ql_dbg_misc, vha, 0xd208,
398 if (vha->hw->fce) {
401 ent->t264.write_pointer = vha->hw->fce_wr;
402 ent->t264.base_pointer = vha->hw->fce_dma;
403 ent->t264.fce_enable_mb0 = vha->hw->fce_mb[0];
404 ent->t264.fce_enable_mb2 = vha->hw->fce_mb[2];
405 ent->t264.fce_enable_mb3 = vha->hw->fce_mb[3];
406 ent->t264.fce_enable_mb4 = vha->hw->fce_mb[4];
407 ent->t264.fce_enable_mb5 = vha->hw->fce_mb[5];
408 ent->t264.fce_enable_mb6 = vha->hw->fce_mb[6];
410 qla27xx_insertbuf(vha->hw->fce, FCE_SIZE, buf, len);
412 ql_dbg(ql_dbg_misc, vha, 0xd027,
421 qla27xx_fwdt_entry_t265(struct scsi_qla_host *vha,
424 ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd209,
427 qla24xx_pause_risc(ISPREG(vha), vha->hw);
433 qla27xx_fwdt_entry_t266(struct scsi_qla_host *vha,
436 ql_dbg(ql_dbg_misc, vha, 0xd20a,
439 WARN_ON_ONCE(qla24xx_soft_reset(vha->hw) != QLA_SUCCESS);
445 qla27xx_fwdt_entry_t267(struct scsi_qla_host *vha,
451 ql_dbg(ql_dbg_misc, vha, 0xd20b,
453 qla27xx_write_reg(ISPREG(vha), offset, data, buf);
459 qla27xx_fwdt_entry_t268(struct scsi_qla_host *vha,
462 ql_dbg(ql_dbg_misc, vha, 0xd20c,
466 if (vha->hw->eft) {
469 ent->t268.start_addr = vha->hw->eft_dma;
471 qla27xx_insertbuf(vha->hw->eft, EFT_SIZE, buf, len);
473 ql_dbg(ql_dbg_misc, vha, 0xd028,
479 if (vha->hw->exchoffld_buf) {
481 ent->t268.buf_size = vha->hw->exchoffld_size;
483 vha->hw->exchoffld_buf_dma;
485 qla27xx_insertbuf(vha->hw->exchoffld_buf,
486 vha->hw->exchoffld_size, buf, len);
488 ql_dbg(ql_dbg_misc, vha, 0xd028,
494 if (vha->hw->exlogin_buf) {
496 ent->t268.buf_size = vha->hw->exlogin_size;
498 vha->hw->exlogin_buf_dma;
500 qla27xx_insertbuf(vha->hw->exlogin_buf,
501 vha->hw->exlogin_size, buf, len);
503 ql_dbg(ql_dbg_misc, vha, 0xd028,
519 ql_dbg(ql_dbg_async, vha, 0xd02b,
529 qla27xx_fwdt_entry_t269(struct scsi_qla_host *vha,
532 ql_dbg(ql_dbg_misc, vha, 0xd20d,
546 qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha,
552 ql_dbg(ql_dbg_misc, vha, 0xd20e,
554 qla27xx_write_reg(ISPREG(vha), IOBASE_ADDR, 0x40, buf);
556 qla27xx_write_reg(ISPREG(vha), 0xc0, addr|0x80000000, buf);
558 qla27xx_read_reg(ISPREG(vha), 0xc4, buf, len);
566 qla27xx_fwdt_entry_t271(struct scsi_qla_host *vha,
572 ql_dbg(ql_dbg_misc, vha, 0xd20f,
574 qla27xx_write_reg(ISPREG(vha), IOBASE(vha), 0x40, buf);
575 qla27xx_write_reg(ISPREG(vha), 0xc4, data, buf);
576 qla27xx_write_reg(ISPREG(vha), 0xc0, addr, buf);
582 qla27xx_fwdt_entry_t272(struct scsi_qla_host *vha,
588 ql_dbg(ql_dbg_misc, vha, 0xd210,
591 ql_dbg(ql_dbg_misc, vha, 0xd02c,
594 qla27xx_dump_mpi_ram(vha->hw, start, buf, dwords, &buf);
602 qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha,
609 ql_dbg(ql_dbg_misc, vha, 0xd211,
613 if (pci_read_config_dword(vha->hw->pdev, addr, &value))
614 ql_dbg(ql_dbg_misc, vha, 0xd02d,
625 qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
632 ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd212,
635 for (i = 0; i < vha->hw->max_req_queues; i++) {
636 struct req_que *req = vha->hw->req_q_map[i];
647 for (i = 0; i < vha->hw->max_rsp_queues; i++) {
648 struct rsp_que *rsp = vha->hw->rsp_q_map[i];
660 struct qla_hw_data *ha = vha->hw;
671 ql_dbg(ql_dbg_misc, vha, 0xd02f,
687 qla27xx_fwdt_entry_t275(struct scsi_qla_host *vha,
695 ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd213,
698 ql_dbg(ql_dbg_misc, vha, 0xd020,
705 ql_dbg(ql_dbg_misc, vha, 0xd030,
716 qla27xx_fwdt_entry_t276(struct scsi_qla_host *vha,
719 ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd214,
725 uint type = vha->hw->pdev->device >> 4 & 0xf;
726 uint func = vha->hw->port_no & 0x3;
741 qla27xx_fwdt_entry_t277(struct scsi_qla_host *vha,
748 ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd215,
751 qla27xx_write_reg(ISPREG(vha), cmd_addr, wr_cmd_data, buf);
752 qla27xx_read_reg(ISPREG(vha), data_addr, buf, len);
758 qla27xx_fwdt_entry_t278(struct scsi_qla_host *vha,
766 ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd216,
768 qla27xx_write_reg(ISPREG(vha), data_addr, wr_data, buf);
769 qla27xx_write_reg(ISPREG(vha), cmd_addr, wr_cmd_data, buf);
775 qla27xx_fwdt_entry_other(struct scsi_qla_host *vha,
780 ql_dbg(ql_dbg_misc, vha, 0xd2ff,
833 qla27xx_walk_template(struct scsi_qla_host *vha,
841 ql_dbg(ql_dbg_misc, vha, 0xd01a,
845 ent = qla27xx_find_entry(type)(vha, ent, buf, len);
851 ql_dbg(ql_dbg_async, vha, 0xffff,
858 ql_dbg(ql_dbg_misc, vha, 0xd018,
862 ql_dbg(ql_dbg_misc, vha, 0xd019,
891 qla27xx_firmware_info(struct scsi_qla_host *vha,
894 tmp->firmware_version[0] = cpu_to_le32(vha->hw->fw_major_version);
895 tmp->firmware_version[1] = cpu_to_le32(vha->hw->fw_minor_version);
896 tmp->firmware_version[2] = cpu_to_le32(vha->hw->fw_subminor_version);
898 vha->hw->fw_attributes_h << 16 | vha->hw->fw_attributes);
900 vha->hw->fw_attributes_ext[1] << 16 | vha->hw->fw_attributes_ext[0]);
904 ql27xx_edit_template(struct scsi_qla_host *vha,
909 qla27xx_firmware_info(vha, tmp);
942 qla27xx_execute_fwdt_template(struct scsi_qla_host *vha,
950 ql27xx_edit_template(vha, tmp);
951 qla27xx_walk_template(vha, tmp, buf, &len);
958 qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *vha, void *p)
965 qla27xx_walk_template(vha, tmp, NULL, &len);
1001 qla27xx_mpi_fwdump(scsi_qla_host_t *vha, int hardware_locked)
1006 spin_lock_irqsave(&vha->hw->hardware_lock, flags);
1007 if (!vha->hw->mpi_fw_dump) {
1008 ql_log(ql_log_warn, vha, 0x02f3, "-> mpi_fwdump no buffer\n");
1010 struct fwdt *fwdt = &vha->hw->fwdt[1];
1012 void *buf = vha->hw->mpi_fw_dump;
1015 if (vha->hw->mpi_fw_dumped) {
1019 ql_log(ql_log_warn, vha, 0x02f4,
1024 ql_log(ql_log_warn, vha, 0x02f5, "-> fwdt1 running...\n");
1026 ql_log(ql_log_warn, vha, 0x02f6,
1030 len = qla27xx_execute_fwdt_template(vha, fwdt->template, buf);
1034 ql_log(ql_log_warn, vha, 0x02f7,
1038 vha->hw->stat.num_mpi_reset++;
1042 vha->hw->mpi_fw_dump_len = len;
1043 vha->hw->mpi_fw_dumped = 1;
1045 ql_log(ql_log_warn, vha, 0x02f8,
1047 vha->host_no, vha->hw->mpi_fw_dump);
1048 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
1053 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
1057 qla27xx_fwdump(scsi_qla_host_t *vha)
1059 lockdep_assert_held(&vha->hw->hardware_lock);
1061 if (!vha->hw->fw_dump) {
1062 ql_log(ql_log_warn, vha, 0xd01e, "-> fwdump no buffer\n");
1063 } else if (vha->hw->fw_dumped) {
1064 ql_log(ql_log_warn, vha, 0xd01f,
1066 vha->hw->fw_dump);
1068 struct fwdt *fwdt = vha->hw->fwdt;
1070 void *buf = vha->hw->fw_dump;
1072 ql_log(ql_log_warn, vha, 0xd011, "-> fwdt0 running...\n");
1074 ql_log(ql_log_warn, vha, 0xd012,
1078 len = qla27xx_execute_fwdt_template(vha, fwdt->template, buf);
1082 ql_log(ql_log_warn, vha, 0xd013,
1087 vha->hw->fw_dump_len = len;
1088 vha->hw->fw_dumped = true;
1090 ql_log(ql_log_warn, vha, 0xd015,
1092 vha->host_no, vha->hw->fw_dump, vha->hw->fw_dump_cap_flags);
1093 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);