Lines Matching refs:vha
46 qla8044_rd_direct(struct scsi_qla_host *vha,
49 struct qla_hw_data *ha = vha->hw;
58 qla8044_wr_direct(struct scsi_qla_host *vha,
62 struct qla_hw_data *ha = vha->hw;
69 qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr)
73 struct qla_hw_data *ha = vha->hw;
79 ql_log(ql_log_warn, vha, 0xb087,
89 qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
92 struct qla_hw_data *ha = vha->hw;
94 ret_val = qla8044_set_win_base(vha, addr);
98 ql_log(ql_log_warn, vha, 0xb088,
104 qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
107 struct qla_hw_data *ha = vha->hw;
109 ret_val = qla8044_set_win_base(vha, addr);
113 ql_log(ql_log_warn, vha, 0xb089,
128 qla8044_read_write_crb_reg(struct scsi_qla_host *vha,
133 qla8044_rd_reg_indirect(vha, raddr, &value);
134 qla8044_wr_reg_indirect(vha, waddr, value);
138 qla8044_poll_wait_for_ready(struct scsi_qla_host *vha, uint32_t addr1,
147 qla8044_rd_reg_indirect(vha, addr1, &temp);
151 ql_log(ql_log_warn, vha, 0xb151,
161 qla8044_ipmdio_rd_reg(struct scsi_qla_host *vha,
167 ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
172 qla8044_wr_reg_indirect(vha, addr1, temp);
174 ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
178 qla8044_rd_reg_indirect(vha, addr3, &ret);
185 qla8044_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *vha,
194 temp = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr2);
198 ql_log(ql_log_warn, vha, 0xb152,
208 qla8044_ipmdio_wr_reg(struct scsi_qla_host *vha, uint32_t addr1,
213 ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
217 qla8044_wr_reg_indirect(vha, addr3, value);
218 qla8044_wr_reg_indirect(vha, addr1, addr);
220 ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
230 * @vha : Pointer to adapter structure
237 qla8044_rmw_crb_reg(struct scsi_qla_host *vha,
243 value = vha->reset_tmplt.array[p_rmw_hdr->index_a];
245 qla8044_rd_reg_indirect(vha, raddr, &value);
251 qla8044_wr_reg_indirect(vha, waddr, value);
256 qla8044_set_qsnt_ready(struct scsi_qla_host *vha)
259 struct qla_hw_data *ha = vha->hw;
261 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
263 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
264 ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n",
265 __func__, vha->host_no, qsnt_state);
269 qla8044_clear_qsnt_ready(struct scsi_qla_host *vha)
272 struct qla_hw_data *ha = vha->hw;
274 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
276 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
277 ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n",
278 __func__, vha->host_no, qsnt_state);
283 * @vha : Pointer to adapter structure
307 qla8044_lock_recovery(struct scsi_qla_host *vha)
310 struct qla_hw_data *ha = vha->hw;
330 ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n"
361 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
384 ql_log(ql_log_warn, vha, 0xb114,
394 ql_dbg(ql_dbg_p3p, vha, 0xb115,
401 if (qla8044_lock_recovery(vha) == QLA_SUCCESS) {
404 ql_dbg(ql_dbg_p3p, vha, 0xb116,
413 ql_dbg(ql_dbg_p3p, vha, 0xb08a,
429 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
434 ql_log(ql_log_warn, vha, 0xb118,
447 qla8044_flash_lock(scsi_qla_host_t *vha)
453 struct qla_hw_data *ha = vha->hw;
463 ql_log(ql_log_warn, vha, 0xb113,
476 qla8044_flash_unlock(scsi_qla_host_t *vha)
478 struct qla_hw_data *ha = vha->hw;
487 void qla8044_flash_lock_recovery(struct scsi_qla_host *vha)
490 if (qla8044_flash_lock(vha)) {
492 ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n");
500 qla8044_flash_unlock(vha);
507 qla8044_read_flash_data(scsi_qla_host_t *vha, uint8_t *p_data,
513 if (qla8044_flash_lock(vha) != QLA_SUCCESS) {
519 ql_log(ql_log_warn, vha, 0xb117,
526 if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW,
528 ql_log(ql_log_warn, vha, 0xb119,
536 ret_val = qla8044_rd_reg_indirect(vha,
540 ql_log(ql_log_warn, vha, 0xb08c,
552 qla8044_flash_unlock(vha);
562 qla8044_read_optrom_data(struct scsi_qla_host *vha, void *buf,
565 scsi_block_requests(vha->host);
566 if (qla8044_read_flash_data(vha, buf, offset, length / 4)
568 ql_log(ql_log_warn, vha, 0xb08d,
572 scsi_unblock_requests(vha->host);
577 qla8044_need_reset(struct scsi_qla_host *vha)
581 struct qla_hw_data *ha = vha->hw;
583 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
584 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
598 * @vha : Pointer to adapter structure
603 qla8044_write_list(struct scsi_qla_host *vha,
613 qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2);
624 * @vha : Pointer to adapter structure
629 qla8044_read_write_list(struct scsi_qla_host *vha,
639 qla8044_read_write_crb_reg(vha, p_entry->arg1,
659 qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr,
667 ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
680 ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
693 vha->reset_tmplt.seq_error++;
694 ql_log(ql_log_fatal, vha, 0xb090,
712 qla8044_poll_list(struct scsi_qla_host *vha,
734 qla8044_poll_reg(vha, p_entry->arg1,
739 if (qla8044_poll_reg(vha,
748 qla8044_rd_reg_indirect(vha,
750 qla8044_rd_reg_indirect(vha,
763 * @vha : Pointer to adapter structure
768 qla8044_poll_write_list(struct scsi_qla_host *vha,
785 qla8044_wr_reg_indirect(vha,
787 qla8044_wr_reg_indirect(vha,
790 if (qla8044_poll_reg(vha,
794 ql_dbg(ql_dbg_p3p, vha, 0xb091,
797 ql_dbg(ql_dbg_p3p, vha, 0xb092,
799 vha->reset_tmplt.seq_index);
810 * @vha : Pointer to adapter structure
815 qla8044_read_modify_write(struct scsi_qla_host *vha,
829 qla8044_rmw_crb_reg(vha, p_entry->arg1,
840 * @vha : Pointer to adapter structure
845 void qla8044_pause(struct scsi_qla_host *vha,
855 * @vha : Pointer to adapter structure
860 qla8044_template_end(struct scsi_qla_host *vha,
863 vha->reset_tmplt.template_end = 1;
865 if (vha->reset_tmplt.seq_error == 0) {
866 ql_dbg(ql_dbg_p3p, vha, 0xb093,
869 ql_log(ql_log_fatal, vha, 0xb094,
880 * @vha : Pointer to adapter structure
885 qla8044_poll_read_list(struct scsi_qla_host *vha,
904 qla8044_wr_reg_indirect(vha, p_entry->ar_addr,
907 if (qla8044_poll_reg(vha, p_entry->ar_addr, delay,
909 ql_dbg(ql_dbg_p3p, vha, 0xb095,
912 ql_dbg(ql_dbg_p3p, vha, 0xb096,
915 vha->reset_tmplt.seq_index);
917 index = vha->reset_tmplt.array_index;
918 qla8044_rd_reg_indirect(vha,
920 vha->reset_tmplt.array[index++] = value;
922 vha->reset_tmplt.array_index = 1;
940 qla8044_process_reset_template(struct scsi_qla_host *vha,
947 vha->reset_tmplt.seq_end = 0;
948 vha->reset_tmplt.template_end = 0;
949 entries = vha->reset_tmplt.hdr->entries;
950 index = vha->reset_tmplt.seq_index;
952 for (; (!vha->reset_tmplt.seq_end) && (index < entries); index++) {
958 qla8044_write_list(vha, p_hdr);
961 qla8044_read_write_list(vha, p_hdr);
964 qla8044_poll_list(vha, p_hdr);
967 qla8044_poll_write_list(vha, p_hdr);
970 qla8044_read_modify_write(vha, p_hdr);
973 qla8044_pause(vha, p_hdr);
976 vha->reset_tmplt.seq_end = 1;
979 qla8044_template_end(vha, p_hdr);
982 qla8044_poll_read_list(vha, p_hdr);
985 ql_log(ql_log_fatal, vha, 0xb097,
995 vha->reset_tmplt.seq_index = index;
999 qla8044_process_init_seq(struct scsi_qla_host *vha)
1001 qla8044_process_reset_template(vha,
1002 vha->reset_tmplt.init_offset);
1003 if (vha->reset_tmplt.seq_end != 1)
1004 ql_log(ql_log_fatal, vha, 0xb098,
1010 qla8044_process_stop_seq(struct scsi_qla_host *vha)
1012 vha->reset_tmplt.seq_index = 0;
1013 qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset);
1014 if (vha->reset_tmplt.seq_end != 1)
1015 ql_log(ql_log_fatal, vha, 0xb099,
1020 qla8044_process_start_seq(struct scsi_qla_host *vha)
1022 qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset);
1023 if (vha->reset_tmplt.template_end != 1)
1024 ql_log(ql_log_fatal, vha, 0xb09a,
1030 qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha,
1042 ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n",
1048 ret_val = qla8044_wr_reg_indirect(vha,
1052 ql_log(ql_log_fatal, vha, 0xb09c,
1063 ret_val = qla8044_rd_reg_indirect(vha,
1066 ql_log(ql_log_fatal, vha, 0xb09d,
1077 ret_val = qla8044_wr_reg_indirect(vha,
1080 ql_log(ql_log_fatal, vha, 0xb09f,
1092 ret_val = qla8044_rd_reg_indirect(vha,
1095 ql_log(ql_log_fatal, vha, 0xb0a0,
1113 * @vha : Pointer to adapter structure
1121 qla8044_ms_mem_write_128b(struct scsi_qla_host *vha,
1127 struct qla_hw_data *ha = vha->hw;
1137 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0);
1139 ql_log(ql_log_fatal, vha, 0xb0a1,
1153 ret_val = qla8044_wr_reg_indirect(vha,
1157 ret_val += qla8044_wr_reg_indirect(vha,
1159 ret_val += qla8044_wr_reg_indirect(vha,
1161 ret_val += qla8044_wr_reg_indirect(vha,
1163 ret_val += qla8044_wr_reg_indirect(vha,
1166 ql_log(ql_log_fatal, vha, 0xb0a2,
1173 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1175 ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1178 ql_log(ql_log_fatal, vha, 0xb0a3,
1184 ret_val = qla8044_rd_reg_indirect(vha,
1187 ql_log(ql_log_fatal, vha, 0xb0a4,
1198 ql_log(ql_log_fatal, vha, 0xb0a5,
1214 qla8044_copy_bootloader(struct scsi_qla_host *vha)
1220 struct qla_hw_data *ha = vha->hw;
1235 ql_log(ql_log_fatal, vha, 0xb0a6,
1242 ret_val = qla8044_lockless_flash_read_u32(vha, src,
1245 ql_log(ql_log_fatal, vha, 0xb0a7,
1249 ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n",
1253 ret_val = qla8044_ms_mem_write_128b(vha, dest,
1256 ql_log(ql_log_fatal, vha, 0xb0a9,
1260 ql_dbg(ql_dbg_p3p, vha, 0xb0aa,
1272 qla8044_restart(struct scsi_qla_host *vha)
1275 struct qla_hw_data *ha = vha->hw;
1277 qla8044_process_stop_seq(vha);
1281 qla8044_get_minidump(vha);
1283 ql_log(ql_log_fatal, vha, 0xb14c,
1286 qla8044_process_init_seq(vha);
1288 if (qla8044_copy_bootloader(vha)) {
1289 ql_log(ql_log_fatal, vha, 0xb0ab,
1301 qla8044_process_start_seq(vha);
1316 qla8044_check_cmd_peg_status(struct scsi_qla_host *vha)
1320 struct qla_hw_data *ha = vha->hw;
1325 ql_dbg(ql_dbg_p3p, vha, 0xb0ac,
1338 qla8044_start_firmware(struct scsi_qla_host *vha)
1342 if (qla8044_restart(vha)) {
1343 ql_log(ql_log_fatal, vha, 0xb0ad,
1349 ql_dbg(ql_dbg_p3p, vha, 0xb0af,
1352 ret_val = qla8044_check_cmd_peg_status(vha);
1354 ql_log(ql_log_fatal, vha, 0xb0b0,
1367 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
1369 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1372 ql_log(ql_log_info, vha, 0xb0b1,
1374 __func__, vha->host_no, drv_active);
1376 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1386 qla8044_device_bootstrap(struct scsi_qla_host *vha)
1393 struct qla_hw_data *ha = vha->hw;
1395 need_reset = qla8044_need_reset(vha);
1398 old_count = qla8044_rd_direct(vha,
1404 count = qla8044_rd_direct(vha,
1411 qla8044_flash_lock_recovery(vha);
1415 qla8044_flash_lock_recovery(vha);
1419 ql_log(ql_log_info, vha, 0xb0b2,
1421 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1425 rval = qla8044_start_firmware(vha);
1429 ql_log(ql_log_info, vha, 0xb0b3,
1432 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1447 ql_log(ql_log_info, vha, 0xb0b4,
1449 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY);
1456 qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha)
1460 if (!vha->reset_tmplt.buff) {
1461 ql_log(ql_log_fatal, vha, 0xb0b5,
1466 phdr = vha->reset_tmplt.buff;
1467 ql_dbg(ql_dbg_p3p, vha, 0xb0b6,
1485 qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha)
1488 uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff;
1489 int u16_count = vha->reset_tmplt.hdr->size / sizeof(uint16_t);
1501 ql_log(ql_log_fatal, vha, 0xb0b7,
1514 qla8044_read_reset_template(struct scsi_qla_host *vha)
1519 vha->reset_tmplt.seq_error = 0;
1520 vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE);
1521 if (vha->reset_tmplt.buff == NULL) {
1522 ql_log(ql_log_fatal, vha, 0xb0b8,
1528 p_buff = vha->reset_tmplt.buff;
1534 ql_dbg(ql_dbg_p3p, vha, 0xb0b9,
1539 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1540 ql_log(ql_log_fatal, vha, 0xb0ba,
1545 vha->reset_tmplt.hdr =
1546 (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff;
1549 tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);
1551 (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) {
1552 ql_log(ql_log_fatal, vha, 0xb0bb,
1559 addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size;
1560 p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size;
1561 tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size -
1562 vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t);
1564 ql_dbg(ql_dbg_p3p, vha, 0xb0bc,
1566 __func__, vha->reset_tmplt.hdr->size);
1569 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1570 ql_log(ql_log_fatal, vha, 0xb0bd,
1576 if (qla8044_reset_seq_checksum_test(vha)) {
1577 ql_log(ql_log_fatal, vha, 0xb0be,
1582 ql_dbg(ql_dbg_p3p, vha, 0xb0bf,
1587 vha->reset_tmplt.init_offset = vha->reset_tmplt.buff +
1588 vha->reset_tmplt.hdr->init_seq_offset;
1590 vha->reset_tmplt.start_offset = vha->reset_tmplt.buff +
1591 vha->reset_tmplt.hdr->start_seq_offset;
1593 vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff +
1594 vha->reset_tmplt.hdr->hdr_size;
1596 qla8044_dump_reset_seq_hdr(vha);
1601 vfree(vha->reset_tmplt.buff);
1608 qla8044_set_idc_dontreset(struct scsi_qla_host *vha)
1611 struct qla_hw_data *ha = vha->hw;
1615 ql_dbg(ql_dbg_p3p, vha, 0xb0c0,
1621 qla8044_set_rst_ready(struct scsi_qla_host *vha)
1624 struct qla_hw_data *ha = vha->hw;
1626 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1632 ql_log(ql_log_info, vha, 0xb0c1,
1634 __func__, vha->host_no, drv_state);
1635 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
1640 * @vha: pointer to adapter structure
1645 qla8044_need_reset_handler(struct scsi_qla_host *vha)
1649 struct qla_hw_data *ha = vha->hw;
1651 ql_log(ql_log_fatal, vha, 0xb0c2,
1654 if (vha->flags.online) {
1656 qla2x00_abort_isp_cleanup(vha);
1657 ha->isp_ops->get_flash_version(vha, vha->req->ring);
1658 ha->isp_ops->nvram_config(vha);
1662 dev_state = qla8044_rd_direct(vha,
1664 drv_state = qla8044_rd_direct(vha,
1666 drv_active = qla8044_rd_direct(vha,
1669 ql_log(ql_log_info, vha, 0xb0c5,
1671 __func__, vha->host_no, drv_state, drv_active, dev_state);
1673 qla8044_set_rst_ready(vha);
1680 ql_log(ql_log_info, vha, 0xb0c4,
1690 dev_state = qla8044_rd_direct(vha,
1692 drv_state = qla8044_rd_direct(vha,
1694 drv_active = qla8044_rd_direct(vha,
1701 ql_log(ql_log_info, vha, 0xb0c7,
1703 __func__, vha->host_no, ha->portnum,
1706 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX,
1716 qla8044_device_bootstrap(vha);
1734 qla8044_device_bootstrap(vha);
1739 qla8044_set_drv_active(struct scsi_qla_host *vha)
1742 struct qla_hw_data *ha = vha->hw;
1744 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1750 ql_log(ql_log_info, vha, 0xb0c8,
1752 __func__, vha->host_no, drv_active);
1753 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1757 qla8044_check_drv_active(struct scsi_qla_host *vha)
1760 struct qla_hw_data *ha = vha->hw;
1762 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1770 qla8044_clear_idc_dontreset(struct scsi_qla_host *vha)
1773 struct qla_hw_data *ha = vha->hw;
1777 ql_log(ql_log_info, vha, 0xb0c9,
1784 qla8044_set_idc_ver(struct scsi_qla_host *vha)
1789 struct qla_hw_data *ha = vha->hw;
1791 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1793 idc_ver = qla8044_rd_direct(vha,
1797 qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX,
1799 ql_log(ql_log_info, vha, 0xb0ca,
1803 idc_ver = qla8044_rd_direct(vha,
1807 ql_log(ql_log_info, vha, 0xb0cb,
1829 qla8044_update_idc_reg(struct scsi_qla_host *vha)
1833 struct qla_hw_data *ha = vha->hw;
1835 if (vha->flags.init_done)
1839 qla8044_set_drv_active(vha);
1841 drv_active = qla8044_rd_direct(vha,
1847 qla8044_clear_idc_dontreset(vha);
1849 rval = qla8044_set_idc_ver(vha);
1860 * @vha: pointer to adapter structure
1863 qla8044_need_qsnt_handler(struct scsi_qla_host *vha)
1867 struct qla_hw_data *ha = vha->hw;
1869 if (vha->flags.online)
1870 qla2x00_quiesce_io(vha);
1874 qla8044_set_qsnt_ready(vha);
1878 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1879 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1890 clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
1891 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1893 qla8044_clear_qsnt_ready(vha);
1894 ql_log(ql_log_info, vha, 0xb0cc,
1902 drv_state = qla8044_rd_direct(vha,
1904 drv_active = qla8044_rd_direct(vha,
1910 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1913 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1915 ql_log(ql_log_info, vha, 0xb0cd,
1927 qla8044_device_state_handler(struct scsi_qla_host *vha)
1932 struct qla_hw_data *ha = vha->hw;
1934 rval = qla8044_update_idc_reg(vha);
1938 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1939 ql_dbg(ql_dbg_p3p, vha, 0xb0ce,
1951 if (qla8044_check_drv_active(vha) == QLA_SUCCESS) {
1952 ql_log(ql_log_warn, vha, 0xb0cf,
1957 qla8044_wr_direct(vha,
1963 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1964 ql_log(ql_log_info, vha, 0xb0d0,
1975 rval = qla8044_device_bootstrap(vha);
1986 qla8044_need_reset_handler(vha);
1990 qla8044_need_qsnt_handler(vha);
1997 ql_log(ql_log_info, vha, 0xb0d1,
2011 qla8xxx_dev_failed_handler(vha);
2017 qla8xxx_dev_failed_handler(vha);
2032 * @vha: adapter block pointer.
2037 qla8044_check_temp(struct scsi_qla_host *vha)
2042 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
2047 ql_log(ql_log_warn, vha, 0xb0d2,
2054 ql_log(ql_log_warn, vha, 0xb0d3,
2062 int qla8044_read_temperature(scsi_qla_host_t *vha)
2066 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
2072 * @vha: Pointer to host adapter structure.
2077 qla8044_check_fw_alive(struct scsi_qla_host *vha)
2083 fw_heartbeat_counter = qla8044_rd_direct(vha,
2088 ql_dbg(ql_dbg_p3p, vha, 0xb0d4,
2091 vha->host_no, __func__);
2095 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
2096 vha->seconds_since_last_heartbeat++;
2098 if (vha->seconds_since_last_heartbeat == 2) {
2099 vha->seconds_since_last_heartbeat = 0;
2100 halt_status1 = qla8044_rd_direct(vha,
2102 halt_status2 = qla8044_rd_direct(vha,
2105 ql_log(ql_log_info, vha, 0xb0d5,
2110 vha->host_no, __func__, halt_status1,
2115 vha->seconds_since_last_heartbeat = 0;
2117 vha->fw_heartbeat_counter = fw_heartbeat_counter;
2122 qla8044_watchdog(struct scsi_qla_host *vha)
2126 struct qla_hw_data *ha = vha->hw;
2129 if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) ||
2130 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) {
2131 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
2133 if (qla8044_check_fw_alive(vha)) {
2135 ql_log(ql_log_warn, vha, 0xb10a,
2137 qla82xx_clear_pending_mbx(vha);
2140 if (qla8044_check_temp(vha)) {
2141 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
2143 qla2xxx_wake_dpc(vha);
2145 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
2146 ql_log(ql_log_info, vha, 0xb0d6,
2149 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2150 qla2xxx_wake_dpc(vha);
2152 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
2153 ql_log(ql_log_info, vha, 0xb0d7,
2156 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
2157 qla2xxx_wake_dpc(vha);
2161 halt_status = qla8044_rd_direct(vha,
2165 ql_log(ql_log_fatal, vha,
2180 &vha->dpc_flags);
2185 &vha->dpc_flags);
2186 ql_log(ql_log_info, vha, 0xb0d9,
2190 ql_log(ql_log_info, vha,
2195 &vha->dpc_flags);
2198 qla2xxx_wake_dpc(vha);
2206 qla8044_minidump_process_control(struct scsi_qla_host *vha,
2215 struct qla_hw_data *ha = vha->hw;
2217 ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__);
2227 qla8044_wr_reg_indirect(vha, crb_addr,
2233 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2234 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2239 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2246 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2249 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2251 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2257 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2268 qla8044_rd_reg_indirect(vha,
2283 qla8044_rd_reg_indirect(vha, addr, &read_value);
2305 qla8044_wr_reg_indirect(vha, addr, read_value);
2327 qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha,
2334 ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__);
2341 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2350 qla8044_minidump_process_rdmem(struct scsi_qla_host *vha,
2358 struct qla_hw_data *ha = vha->hw;
2360 ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__);
2365 ql_dbg(ql_dbg_p3p, vha, 0xb0f0,
2370 ql_dbg(ql_dbg_p3p, vha, 0xb0f1,
2377 ql_dbg(ql_dbg_p3p, vha, 0xb0f2,
2383 ql_dbg(ql_dbg_p3p, vha, 0xb0f3,
2389 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr);
2391 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value);
2393 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2395 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2398 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
2410 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j],
2419 ql_dbg(ql_dbg_p3p, vha, 0xb0f4,
2429 qla8044_minidump_process_rdrom(struct scsi_qla_host *vha,
2440 ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2443 rval = qla8044_lockless_flash_read_u32(vha, fl_addr,
2447 ql_log(ql_log_fatal, vha, 0xb0f6,
2458 qla8044_mark_entry_skipped(struct scsi_qla_host *vha,
2463 ql_log(ql_log_info, vha, 0xb0f7,
2465 vha->host_no, index, entry_hdr->entry_type,
2470 qla8044_minidump_process_l2tag(struct scsi_qla_host *vha,
2482 ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__);
2497 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2499 qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2504 qla8044_rd_reg_indirect(vha, c_addr,
2517 qla8044_rd_reg_indirect(vha, addr, &r_value);
2528 qla8044_minidump_process_l1cache(struct scsi_qla_host *vha,
2548 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2549 qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2552 qla8044_rd_reg_indirect(vha, addr, &r_value);
2562 qla8044_minidump_process_rdocm(struct scsi_qla_host *vha,
2568 struct qla_hw_data *ha = vha->hw;
2570 ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__);
2577 ql_dbg(ql_dbg_p3p, vha, 0xb0fa,
2586 ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n",
2593 qla8044_minidump_process_rdmux(struct scsi_qla_host *vha,
2601 ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__);
2611 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2612 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2621 qla8044_minidump_process_queue(struct scsi_qla_host *vha,
2631 ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__);
2639 qla8044_wr_reg_indirect(vha, s_addr, qid);
2642 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2653 qla8044_minidump_process_pollrd(struct scsi_qla_host *vha,
2672 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2675 qla8044_rd_reg_indirect(vha, s_addr, &r_value);
2681 ql_log(ql_log_fatal, vha, 0xb0fe,
2687 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2701 qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha,
2718 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1);
2722 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2723 qla8044_rd_reg_indirect(vha, read_addr, &data);
2727 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2);
2731 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2732 qla8044_rd_reg_indirect(vha, read_addr, &data);
2744 qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha,
2760 qla8044_wr_reg_indirect(vha, addr_1, value_1);
2764 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2771 ql_log(ql_log_fatal, vha, 0xb0ff,
2778 qla8044_rd_reg_indirect(vha, addr_2, &data);
2780 qla8044_wr_reg_indirect(vha, addr_2, data);
2781 qla8044_wr_reg_indirect(vha, addr_1, value_2);
2785 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2792 ql_log(ql_log_fatal, vha, 0xb100,
2821 qla8044_check_dma_engine_state(struct scsi_qla_host *vha)
2823 struct qla_hw_data *ha = vha->hw;
2836 rval = qla8044_rd_reg_indirect(vha,
2850 qla8044_start_pex_dma(struct scsi_qla_host *vha,
2853 struct qla_hw_data *ha = vha->hw;
2865 rval = qla8044_wr_reg_indirect(vha,
2871 rval = qla8044_wr_reg_indirect(vha,
2876 rval = qla8044_wr_reg_indirect(vha,
2884 rval = qla8044_rd_reg_indirect(vha,
2907 qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha,
2910 struct qla_hw_data *ha = vha->hw;
2919 rval = qla8044_check_dma_engine_state(vha);
2921 ql_dbg(ql_dbg_p3p, vha, 0xb147,
2931 ql_dbg(ql_dbg_p3p, vha, 0xb148,
2966 rval = qla8044_ms_mem_write_128b(vha,
2970 ql_log(ql_log_warn, vha, 0xb14a,
2975 ql_dbg(ql_dbg_p3p, vha, 0xb14b,
2980 rval = qla8044_start_pex_dma(vha, m_hdr);
3000 qla8044_minidump_process_rddfe(struct scsi_qla_host *vha,
3027 qla8044_wr_reg_indirect(vha, addr1, (0x40000000 | value));
3031 qla8044_rd_reg_indirect(vha, addr1, &temp);
3038 ql_log(ql_log_warn, vha, 0xb153,
3042 qla8044_rd_reg_indirect(vha, addr2, &temp);
3047 qla8044_wr_reg_indirect(vha, addr2, wrVal);
3048 qla8044_wr_reg_indirect(vha, addr1, value);
3052 qla8044_rd_reg_indirect(vha, addr1, &temp);
3058 ql_log(ql_log_warn, vha, 0xb154,
3063 qla8044_wr_reg_indirect(vha, addr1,
3067 qla8044_rd_reg_indirect(vha, addr1, &temp);
3074 ql_log(ql_log_warn, vha, 0xb155,
3079 qla8044_rd_reg_indirect(vha, addr2, &data);
3096 qla8044_minidump_process_rdmdio(struct scsi_qla_host *vha,
3124 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
3130 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr4,
3136 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr5,
3142 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask,
3147 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
3153 data = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr7);
3173 static uint32_t qla8044_minidump_process_pollwr(struct scsi_qla_host *vha,
3189 qla8044_rd_reg_indirect(vha, addr1, &r_value);
3197 ql_log(ql_log_warn, vha, 0xb156, "%s: TIMEOUT\n", __func__);
3201 qla8044_wr_reg_indirect(vha, addr2, value2);
3202 qla8044_wr_reg_indirect(vha, addr1, value1);
3206 qla8044_rd_reg_indirect(vha, addr1, &r_value);
3225 qla8044_collect_md_data(struct scsi_qla_host *vha)
3235 struct qla_hw_data *ha = vha->hw;
3238 ql_log(ql_log_info, vha, 0xb101,
3240 __func__, vha->host_no);
3245 ql_log(ql_log_warn, vha, 0xb10d,
3254 ql_log(ql_log_warn, vha, 0xb10e,
3262 ql_log(ql_log_warn, vha, 0xb112,
3273 if (qla82xx_validate_template_chksum(vha)) {
3274 ql_log(ql_log_info, vha, 0xb109,
3284 ql_dbg(ql_dbg_p3p, vha, 0xb11a,
3291 ql_log(ql_log_warn, vha, 0xb10f,
3297 ql_log(ql_log_info, vha, 0xb102,
3300 ql_log(ql_log_info, vha, 0xb10b,
3303 ql_log(ql_log_info, vha, 0xb10c,
3320 ql_log(ql_log_info, vha, 0xb103,
3334 ql_dbg(ql_dbg_p3p, vha, 0xb104,
3344 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3347 rval = qla8044_minidump_process_control(vha,
3350 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3355 qla8044_minidump_process_rdcrb(vha,
3359 rval = qla8044_minidump_pex_dma_read(vha,
3362 rval = qla8044_minidump_process_rdmem(vha,
3365 qla8044_mark_entry_skipped(vha,
3373 rval = qla8044_minidump_process_rdrom(vha,
3376 qla8044_mark_entry_skipped(vha,
3384 rval = qla8044_minidump_process_l2tag(vha,
3387 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3395 qla8044_minidump_process_l1cache(vha,
3399 qla8044_minidump_process_rdocm(vha,
3403 qla8044_minidump_process_rdmux(vha,
3407 qla8044_minidump_process_queue(vha,
3411 rval = qla8044_minidump_process_pollrd(vha,
3414 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3417 qla8044_minidump_process_rdmux2(vha,
3421 rval = qla8044_minidump_process_pollrdmwr(vha,
3424 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3427 rval = qla8044_minidump_process_rddfe(vha, entry_hdr,
3430 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3433 rval = qla8044_minidump_process_rdmdio(vha, entry_hdr,
3436 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3439 rval = qla8044_minidump_process_pollwr(vha, entry_hdr,
3442 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3446 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3461 ql_log(ql_log_info, vha, 0xb105,
3469 ql_log(ql_log_info, vha, 0xb110,
3471 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
3473 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
3476 ql_log(ql_log_info, vha, 0xb106,
3484 qla8044_get_minidump(struct scsi_qla_host *vha)
3486 struct qla_hw_data *ha = vha->hw;
3488 if (!qla8044_collect_md_data(vha)) {
3492 ql_log(ql_log_fatal, vha, 0xb0db,
3500 qla8044_poll_flash_status_reg(struct scsi_qla_host *vha)
3507 ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS,
3510 ql_log(ql_log_warn, vha, 0xb13c,
3528 qla8044_write_flash_status_reg(struct scsi_qla_host *vha,
3534 cmd = vha->hw->fdt_wrt_sts_reg_cmd;
3536 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3539 ql_log(ql_log_warn, vha, 0xb125,
3544 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data);
3546 ql_log(ql_log_warn, vha, 0xb126,
3551 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3554 ql_log(ql_log_warn, vha, 0xb127,
3559 ret_val = qla8044_poll_flash_status_reg(vha);
3561 ql_log(ql_log_warn, vha, 0xb128,
3572 qla8044_unprotect_flash(scsi_qla_host_t *vha)
3575 struct qla_hw_data *ha = vha->hw;
3577 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable);
3579 ql_log(ql_log_warn, vha, 0xb139,
3589 qla8044_protect_flash(scsi_qla_host_t *vha)
3592 struct qla_hw_data *ha = vha->hw;
3594 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable);
3596 ql_log(ql_log_warn, vha, 0xb13b,
3604 qla8044_erase_flash_sector(struct scsi_qla_host *vha,
3610 ret_val = qla8044_poll_flash_status_reg(vha);
3612 ql_log(ql_log_warn, vha, 0xb12e,
3620 ret_val = qla8044_wr_reg_indirect(vha,
3623 ql_log(ql_log_warn, vha, 0xb12f,
3626 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3627 QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd);
3629 ql_log(ql_log_warn, vha, 0xb130,
3632 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3635 ql_log(ql_log_warn, vha, 0xb131,
3638 ret_val = qla8044_poll_flash_status_reg(vha);
3640 ql_log(ql_log_warn, vha, 0xb132,
3660 qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr,
3665 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3668 ql_log(ql_log_warn, vha, 0xb134,
3672 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data);
3674 ql_log(ql_log_warn, vha, 0xb135,
3678 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D);
3680 ql_log(ql_log_warn, vha, 0xb136,
3684 ret_val = qla8044_poll_flash_status_reg(vha);
3686 ql_log(ql_log_warn, vha, 0xb137,
3695 qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3703 ql_dbg(ql_dbg_user, vha, 0xb123,
3709 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val);
3710 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3712 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3716 ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA,
3718 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3721 ret = qla8044_poll_flash_status_reg(vha);
3723 ql_log(ql_log_warn, vha, 0xb124,
3730 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3736 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3737 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3739 ret = qla8044_poll_flash_status_reg(vha);
3741 ql_log(ql_log_warn, vha, 0xb129,
3748 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3752 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3753 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3755 ret = qla8044_poll_flash_status_reg(vha);
3757 ql_log(ql_log_warn, vha, 0xb12a,
3761 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val);
3764 ql_log(ql_log_warn, vha, 0xb12b,
3768 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3770 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3778 qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3785 ret = qla8044_flash_write_u32(vha, faddr, dwptr);
3787 ql_dbg(ql_dbg_p3p, vha, 0xb141,
3798 qla8044_write_optrom_data(struct scsi_qla_host *vha, void *buf,
3822 scsi_block_requests(vha->host);
3824 qla8044_flash_lock(vha);
3825 qla8044_unprotect_flash(vha);
3829 rval = qla8044_erase_flash_sector(vha, erase_offset);
3830 ql_dbg(ql_dbg_user, vha, 0xb138,
3834 ql_log(ql_log_warn, vha, 0xb121,
3841 ql_dbg(ql_dbg_user, vha, 0xb13f,
3848 rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src,
3852 ql_log(ql_log_warn, vha, 0xb122,
3855 rval = qla8044_write_flash_dword_mode(vha,
3862 ql_dbg(ql_dbg_user, vha, 0xb133,
3866 qla8044_protect_flash(vha);
3867 qla8044_flash_unlock(vha);
3868 scsi_unblock_requests(vha->host);
3889 scsi_qla_host_t *vha;
3907 vha = pci_get_drvdata(ha->pdev);
3916 ql_dbg(ql_dbg_p3p, vha, 0xb144,
3925 ql_dbg(ql_dbg_p3p, vha, 0xb145,
3958 qla82xx_mbx_completion(vha, MSW(stat));
3966 qla2x00_async_event(vha, rsp, mb);
3969 qla24xx_process_response_queue(vha, rsp);
3972 ql_dbg(ql_dbg_p3p, vha, 0xb146,
3997 qla8044_clear_rst_ready(scsi_qla_host_t *vha)
4001 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
4008 drv_state &= ~(1 << vha->hw->portnum);
4010 ql_dbg(ql_dbg_p3p, vha, 0xb13d,
4012 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
4016 qla8044_abort_isp(scsi_qla_host_t *vha)
4020 struct qla_hw_data *ha = vha->hw;
4023 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
4026 qla8044_set_idc_dontreset(vha);
4038 ql_dbg(ql_dbg_p3p, vha, 0xb13e,
4044 ql_dbg(ql_dbg_p3p, vha, 0xb140,
4046 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
4053 qla83xx_reset_ownership(vha);
4056 rval = qla8044_device_state_handler(vha);
4058 qla8044_clear_rst_ready(vha);
4065 rval = qla82xx_restart_isp(vha);
4072 qla8044_fw_dump(scsi_qla_host_t *vha)
4074 struct qla_hw_data *ha = vha->hw;
4079 scsi_block_requests(vha->host);
4082 qla82xx_set_reset_owner(vha);
4084 qla2x00_wait_for_chip_reset(vha);
4085 scsi_unblock_requests(vha->host);