Lines Matching refs:addr
34 qla8044_rd_reg(struct qla_hw_data *ha, ulong addr)
36 return readl((void __iomem *) (ha->nx_pcibase + addr));
40 qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val)
42 writel(val, (void __iomem *)((ha)->nx_pcibase + addr));
69 qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr)
75 qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr);
78 if (val != addr) {
81 "addr written 0x%x, read 0x%x!\n",
82 __func__, addr, val);
89 qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
94 ret_val = qla8044_set_win_base(vha, addr);
99 "%s: failed read of addr 0x%x!\n", __func__, addr);
104 qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
109 ret_val = qla8044_set_win_base(vha, addr);
114 "%s: failed wrt to addr 0x%x, data 0x%x\n",
115 __func__, addr, data);
162 uint32_t addr1, uint32_t addr3, uint32_t mask, uint32_t addr)
171 temp = (0x40000000 | addr);
209 uint32_t addr3, uint32_t mask, uint32_t addr, uint32_t value)
218 qla8044_wr_reg_indirect(vha, addr1, addr);
520 "%s: Illegal addr = 0x%x\n", __func__, flash_addr);
529 "%s: failed to write addr 0x%x to "
541 "%s: failed to read addr 0x%x!\n",
647 * qla8044_poll_reg - Poll the given CRB addr for duration msecs till
651 * @addr : CRB register address
659 qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr,
667 ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
680 ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
1036 uint32_t addr = flash_addr;
1039 flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1);
1041 if (addr & 0x3) {
1042 ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n",
1043 __func__, addr);
1049 QLA8044_FLASH_DIRECT_WINDOW, (addr));
1053 "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
1054 __func__, addr);
1064 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
1067 "%s: failed to read addr 0x%x!\n",
1068 __func__, addr);
1073 addr = addr + 4;
1078 QLA8044_FLASH_DIRECT_WINDOW, (addr));
1081 "%s: failed to write addr "
1083 __func__, addr);
1093 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
1096 "%s: failed to read addr 0x%x!\n",
1097 __func__, addr);
1102 addr = addr + 4;
1114 * addr : Flash address to write to
1122 uint64_t addr, uint32_t *data, uint32_t count)
1130 if (addr & 0xF) {
1144 for (i = 0; i < count; i++, addr += 16) {
1145 if (!((addr_in_range(addr, QLA8044_ADDR_QDR_NET,
1147 (addr_in_range(addr, QLA8044_ADDR_DDR_NET,
1154 MD_MIU_TEST_AGT_ADDR_LO, addr);
1517 uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size;
1529 addr = QLA8044_RESET_TEMPLATE_ADDR;
1539 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1559 addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size;
1569 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
2210 uint32_t read_value, opcode, poll_time, addr, index;
2222 crb_addr = crb_entry->addr;
2278 addr = tmplt_hdr->saved_state_array[index];
2280 addr = crb_addr;
2283 qla8044_rd_reg_indirect(vha, addr, &read_value);
2292 addr = tmplt_hdr->saved_state_array[index];
2294 addr = crb_addr;
2305 qla8044_wr_reg_indirect(vha, addr, read_value);
2336 r_addr = crb_hdr->addr;
2366 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2371 "[%s]: Read addr 0x%x not 16 bytes aligned\n",
2474 uint32_t addr, r_addr, c_addr, t_r_addr;
2515 addr = r_addr;
2517 qla8044_rd_reg_indirect(vha, addr, &r_value);
2519 addr += cache_hdr->read_ctrl.read_addr_stride;
2531 uint32_t addr, r_addr, c_addr, t_r_addr;
2550 addr = r_addr;
2552 qla8044_rd_reg_indirect(vha, addr, &r_value);
2554 addr += cache_hdr->read_ctrl.read_addr_stride;
3652 * addr : Flash address to write to
3660 qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr,
3666 0x00800000 | (addr >> 2));
3842 "Got write for addr = 0x%x length=0x%x.\n",