Lines Matching refs:r_addr
3803 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3808 r_addr = ocm_hdr->read_addr;
3813 r_value = rd_reg_dword(r_addr + ha->nx_pcibase);
3815 r_addr += r_stride;
3825 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3830 r_addr = mux_hdr->read_addr;
3838 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3851 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3856 r_addr = crb_hdr->addr;
3861 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3862 *data_ptr++ = cpu_to_le32(r_addr);
3864 r_addr += r_stride;
3874 uint32_t addr, r_addr, c_addr, t_r_addr;
3884 r_addr = cache_hdr->read_addr;
3916 addr = r_addr;
3933 uint32_t addr, r_addr, c_addr, t_r_addr;
3941 r_addr = cache_hdr->read_addr;
3952 addr = r_addr;
3968 uint32_t s_addr, r_addr;
3982 r_addr = q_hdr->read_addr;
3984 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3986 r_addr += r_stride;
3998 uint32_t r_addr, r_value;
4004 r_addr = rom_hdr->read_addr;
4009 (r_addr & 0xFFFF0000), 1);
4012 (r_addr & 0x0000FFFF), 0, 0);
4014 r_addr += sizeof(uint32_t);
4024 uint32_t r_addr, r_value, r_data;
4032 r_addr = m_hdr->read_addr;
4035 if (r_addr & 0xf) {
4037 "Read addr 0x%x not 16 bytes aligned\n", r_addr);
4050 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4054 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4081 r_addr += 16;