Lines Matching refs:ctrl_status
2474 ha->pci_attr = rd_reg_word(®->ctrl_status);
2525 wrt_reg_word(®->ctrl_status, 0x20);
2526 rd_reg_word(®->ctrl_status);
2535 wrt_reg_word(®->ctrl_status, 0x0);
2536 rd_reg_word(®->ctrl_status);
2556 ha->pci_attr = rd_reg_word(®->ctrl_status);
2600 ha->pci_attr = rd_reg_dword(®->ctrl_status);
2718 wrt_reg_word(®->ctrl_status, 0x20);
2719 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2732 wrt_reg_word(®->ctrl_status, 0x10);
2733 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2751 wrt_reg_word(®->ctrl_status, 0);
2752 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2767 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
2778 if ((rd_reg_word(®->ctrl_status) &
2857 wrt_reg_dword(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2859 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2865 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE))
2871 rd_reg_dword(®->ctrl_status),
2872 (rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE));
2874 wrt_reg_dword(®->ctrl_status,
2900 rd_reg_dword(®->ctrl_status);
2903 if ((rd_reg_dword(®->ctrl_status) &
2909 if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET))
2915 rd_reg_dword(®->ctrl_status));
3105 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
3112 data = qla2x00_debounce_register(®->ctrl_status);
3115 data = rd_reg_word(®->ctrl_status);
4720 if ((rd_reg_word(®->ctrl_status) >> 14) == 1)