Lines Matching refs:mb
1118 uint16_t mb[MAILBOX_REGISTER_COUNT];
1127 mb[0] = MBC_SET_TARGET_PARAMETERS;
1128 mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8);
1129 mb[2] = nv->bus[bus].target[target].parameter.renegotiate_on_error << 8;
1130 mb[2] |= nv->bus[bus].target[target].parameter.stop_queue_on_check << 9;
1131 mb[2] |= nv->bus[bus].target[target].parameter.auto_request_sense << 10;
1132 mb[2] |= nv->bus[bus].target[target].parameter.tag_queuing << 11;
1133 mb[2] |= nv->bus[bus].target[target].parameter.enable_sync << 12;
1134 mb[2] |= nv->bus[bus].target[target].parameter.enable_wide << 13;
1135 mb[2] |= nv->bus[bus].target[target].parameter.parity_checking << 14;
1136 mb[2] |= nv->bus[bus].target[target].parameter.disconnect_allowed << 15;
1139 mb[2] |= nv->bus[bus].target[target].ppr_1x160.flags.enable_ppr << 5;
1140 mb[3] = (nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8);
1141 mb[6] = (nv->bus[bus].target[target].ppr_1x160.flags.ppr_options << 8) |
1145 mb[3] = (nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8);
1147 mb[3] |= nv->bus[bus].target[target].sync_period;
1149 status = qla1280_mailbox_command(ha, mr, mb);
1153 mb[0] = MBC_SET_DEVICE_QUEUE;
1154 mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8);
1155 mb[1] |= lun;
1156 mb[2] = nv->bus[bus].max_queue_depth;
1157 mb[3] = nv->bus[bus].target[target].execution_throttle;
1158 status |= qla1280_mailbox_command(ha, 0x0f, mb);
1555 uint16_t mb[MAILBOX_REGISTER_COUNT];
1635 mb[0] = MBC_MAILBOX_REGISTER_TEST;
1636 mb[1] = 0xAAAA;
1637 mb[2] = 0x5555;
1638 mb[3] = 0xAA55;
1639 mb[4] = 0x55AA;
1640 mb[5] = 0xA5A5;
1641 mb[6] = 0x5A5A;
1642 mb[7] = 0x2525;
1644 status = qla1280_mailbox_command(ha, 0xff, mb);
1648 if (mb[1] != 0xAAAA || mb[2] != 0x5555 || mb[3] != 0xAA55 ||
1649 mb[4] != 0x55AA || mb[5] != 0xA5A5 || mb[6] != 0x5A5A ||
1650 mb[7] != 0x2525) {
1670 uint16_t mb[MAILBOX_REGISTER_COUNT], i;
1686 mb[0] = MBC_WRITE_RAM_WORD;
1687 mb[1] = risc_address + i;
1688 mb[2] = __le16_to_cpu(fw_data[i]);
1690 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb);
1719 uint16_t mb[MAILBOX_REGISTER_COUNT], cnt;
1760 mb[0] = LOAD_CMD;
1761 mb[1] = risc_address;
1762 mb[4] = cnt;
1763 mb[3] = ha->request_dma & 0xffff;
1764 mb[2] = (ha->request_dma >> 16) & 0xffff;
1765 mb[7] = upper_32_bits(ha->request_dma) & 0xffff;
1766 mb[6] = upper_32_bits(ha->request_dma) >> 16;
1768 __func__, mb[0],
1770 mb[6], mb[7], mb[2], mb[3]);
1771 err = qla1280_mailbox_command(ha, CMD_ARGS, mb);
1779 mb[0] = DUMP_CMD;
1780 mb[1] = risc_address;
1781 mb[4] = cnt;
1782 mb[3] = p_tbuf & 0xffff;
1783 mb[2] = (p_tbuf >> 16) & 0xffff;
1784 mb[7] = upper_32_bits(p_tbuf) & 0xffff;
1785 mb[6] = upper_32_bits(p_tbuf) >> 16;
1787 err = qla1280_mailbox_command(ha, CMD_ARGS, mb);
1822 uint16_t mb[MAILBOX_REGISTER_COUNT];
1829 mb[0] = MBC_VERIFY_CHECKSUM;
1830 /* mb[1] = ql12_risc_code_addr01; */
1831 mb[1] = ha->fwstart;
1832 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
1840 mb[0] = MBC_EXECUTE_FIRMWARE;
1841 mb[1] = ha->fwstart;
1842 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
1887 uint16_t mb[MAILBOX_REGISTER_COUNT];
1900 /* mb[0] = MBC_INIT_REQUEST_QUEUE; */
1901 mb[0] = MBC_INIT_REQUEST_QUEUE_A64;
1902 mb[1] = REQUEST_ENTRY_CNT;
1903 mb[3] = ha->request_dma & 0xffff;
1904 mb[2] = (ha->request_dma >> 16) & 0xffff;
1905 mb[4] = 0;
1906 mb[7] = upper_32_bits(ha->request_dma) & 0xffff;
1907 mb[6] = upper_32_bits(ha->request_dma) >> 16;
1910 &mb[0]))) {
1914 /* mb[0] = MBC_INIT_RESPONSE_QUEUE; */
1915 mb[0] = MBC_INIT_RESPONSE_QUEUE_A64;
1916 mb[1] = RESPONSE_ENTRY_CNT;
1917 mb[3] = ha->response_dma & 0xffff;
1918 mb[2] = (ha->response_dma >> 16) & 0xffff;
1919 mb[5] = 0;
1920 mb[7] = upper_32_bits(ha->response_dma) & 0xffff;
1921 mb[6] = upper_32_bits(ha->response_dma) >> 16;
1924 &mb[0]);
2073 uint16_t mb[MAILBOX_REGISTER_COUNT];
2078 mb[0] = MBC_SET_TARGET_PARAMETERS;
2079 mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8);
2086 mb[2] = (TP_RENEGOTIATE | TP_AUTO_REQUEST_SENSE | TP_TAGGED_QUEUE
2090 mb[3] = nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8;
2092 mb[3] = nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8;
2093 mb[3] |= nv->bus[bus].target[target].sync_period;
2094 status = qla1280_mailbox_command(ha, 0x0f, mb);
2116 mb[0] = MBC_SET_DEVICE_QUEUE;
2117 mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8);
2118 mb[1] |= lun;
2119 mb[2] = nv->bus[bus].max_queue_depth;
2120 mb[3] = nv->bus[bus].target[target].execution_throttle;
2121 status |= qla1280_mailbox_command(ha, 0x0f, mb);
2131 uint16_t mb[MAILBOX_REGISTER_COUNT];
2140 mb[0] = MBC_SET_INITIATOR_ID;
2141 mb[1] = bus ? ha->bus_settings[bus].id | BIT_7 :
2143 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
2165 uint16_t mb[MAILBOX_REGISTER_COUNT];
2226 mb[0] = MBC_SET_SYSTEM_PARAMETER;
2227 mb[1] = nv->isp_parameter;
2228 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
2232 mb[0] = MBC_SET_CLOCK_RATE;
2233 mb[1] = 40;
2234 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2238 mb[0] = MBC_SET_FIRMWARE_FEATURES;
2239 mb[1] = nv->firmware_feature.f.enable_fast_posting;
2240 mb[1] |= nv->firmware_feature.f.report_lvd_bus_transition << 1;
2241 mb[1] |= nv->firmware_feature.f.disable_synchronous_backoff << 5;
2242 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2245 mb[0] = MBC_SET_RETRY_COUNT;
2246 mb[1] = nv->bus[0].retry_count;
2247 mb[2] = nv->bus[0].retry_delay;
2248 mb[6] = nv->bus[1].retry_count;
2249 mb[7] = nv->bus[1].retry_delay;
2251 BIT_1 | BIT_0, &mb[0]);
2254 mb[0] = MBC_SET_ASYNC_DATA_SETUP;
2255 mb[1] = nv->bus[0].config_2.async_data_setup_time;
2256 mb[2] = nv->bus[1].config_2.async_data_setup_time;
2257 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
2260 mb[0] = MBC_SET_ACTIVE_NEGATION;
2261 mb[1] = 0;
2263 mb[1] |= BIT_5;
2265 mb[1] |= BIT_4;
2266 mb[2] = 0;
2268 mb[2] |= BIT_5;
2270 mb[2] |= BIT_4;
2271 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2273 mb[0] = MBC_SET_DATA_OVERRUN_RECOVERY;
2274 mb[1] = 2; /* Reset SCSI bus and return all outstanding IO */
2275 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2278 mb[0] = MBC_SET_PCI_CONTROL;
2279 mb[1] = BIT_1; /* Data DMA Channel Burst Enable */
2280 mb[2] = BIT_1; /* Command DMA Channel Burst Enable */
2281 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2283 mb[0] = MBC_SET_TAG_AGE_LIMIT;
2284 mb[1] = 8;
2285 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2288 mb[0] = MBC_SET_SELECTION_TIMEOUT;
2289 mb[1] = nv->bus[0].selection_timeout;
2290 mb[2] = nv->bus[1].selection_timeout;
2291 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2412 * mb = data pointer for mailbox registers.
2415 * mb[MAILBOX_REGISTER_COUNT] = returned mailbox data.
2421 qla1280_mailbox_command(struct scsi_qla_host *ha, uint8_t mr, uint16_t *mb)
2443 iptr = mb;
2476 mb[0], ha->mailbox_out[0], RD_REG_WORD(®->istatus));
2487 optr = mb;
2497 "0x%x ****\n", mb[0]);
2549 uint16_t mb[MAILBOX_REGISTER_COUNT];
2560 mb[0] = MBC_BUS_RESET;
2561 mb[1] = reset_delay;
2562 mb[2] = (uint16_t) bus;
2563 status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
2609 uint16_t mb[MAILBOX_REGISTER_COUNT];
2614 mb[0] = MBC_ABORT_TARGET;
2615 mb[1] = (bus ? (target | BIT_7) : target) << 8;
2616 mb[2] = 1;
2617 status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
2643 uint16_t mb[MAILBOX_REGISTER_COUNT];
2655 mb[0] = MBC_ABORT_COMMAND;
2656 mb[1] = (bus ? target | BIT_7 : target) << 8 | lun;
2657 mb[2] = handle >> 16;
2658 mb[3] = handle & 0xffff;
2659 status = qla1280_mailbox_command(ha, 0x0f, &mb[0]);
3892 uint16_t mb[MAILBOX_REGISTER_COUNT];
3900 mb[0] = MBC_GET_TARGET_PARAMETERS;
3901 mb[1] = (uint16_t) (bus ? target | BIT_7 : target);
3902 mb[1] <<= 8;
3904 &mb[0]);
3908 if (mb[3] != 0) {
3910 (mb[3] & 0xff), (mb[3] >> 8));
3911 if (mb[2] & BIT_13)
3913 if ((mb[2] & BIT_5) && ((mb[6] >> 8) & 0xff) >= 2)