Lines Matching refs:regVal
390 u32 regVal;
399 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
400 } while ((regVal != shiftValue) && time_before(jiffies, start));
402 if (regVal != shiftValue) {
405 regVal);
759 u32 regVal, regVal1, regVal2;
765 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
767 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
785 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
787 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
814 u32 regVal, toggleVal;
836 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
838 regVal);
847 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
849 regVal);
852 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
854 regVal);
857 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
859 regVal);
860 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
862 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
864 regVal);
867 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
868 pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal);
869 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
872 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
874 toggleVal = regVal ^ SCRATCH_PAD1_RST;
893 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
902 regVal &= ~(0x00003b00);
904 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
948 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
950 regVal);
952 regVal &= 0xFFFFFFFC;
953 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
963 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
965 regVal);
966 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
967 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
970 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
972 regVal);
973 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
974 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
980 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
983 regVal);
984 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
985 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1001 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1010 regVal |= (GSM_CONFIG_RESET_VALUE);
1011 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1016 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1020 regVal);
1025 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1031 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1045 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1046 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1047 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1058 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1060 } while ((regVal != toggleVal) && (--max_wait_count));
1063 regVal = pm8001_cr32(pm8001_ha, 0,
1066 toggleVal, regVal);
1091 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1095 regVal);
1096 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1100 regVal);
1123 u32 regVal;
1127 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1128 regVal &= ~(SPC_REG_RESET_DEVICE);
1129 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1135 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1136 regVal |= SPC_REG_RESET_DEVICE;
1137 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);