Lines Matching refs:data
357 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
358 int pos = data->msgout_len;
366 data->msgoutbuf[pos] = IDENTIFY(mode, SCpnt->device->lun); pos++;
368 data->msgout_len = pos;
378 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
379 int pos = data->msgout_len;
381 data->msgoutbuf[pos] = EXTENDED_MESSAGE; pos++;
382 data->msgoutbuf[pos] = EXTENDED_SDTR_LEN; pos++;
383 data->msgoutbuf[pos] = EXTENDED_SDTR; pos++;
384 data->msgoutbuf[pos] = period; pos++;
385 data->msgoutbuf[pos] = offset; pos++;
387 data->msgout_len = pos;
395 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
396 int pos = data->msgout_len;
404 data->msgoutbuf[pos] = NOP; pos++;
405 data->msgout_len = pos;
413 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
414 int pos = data->msgout_len;
416 data->msgoutbuf[pos] = MESSAGE_REJECT; pos++;
417 data->msgout_len = pos;
444 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
448 nsp32_autoparam *param = data->autoparam;
473 if (data->msgout_len == 0) {
477 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
479 for (i = 0; i < data->msgout_len; i++) {
487 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
490 msgout |= (unsigned int)data->msgout_len; /* len */
492 /* data->msgout_len > 3 */
513 param->syncreg = data->cur_target->syncreg;
514 param->ackwidth = data->cur_target->ackwidth;
516 param->sample_reg = data->cur_target->sample_reg;
518 // nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "sample rate=0x%x\n", data->cur_target->sample_reg);
530 switch (data->trans_method) {
552 param->sgt_pointer = cpu_to_le32(data->cur_lunt->sglun_paddr);
557 nsp32_write4(base, SGT_ADR, data->auto_paddr);
575 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
633 if (data->msgout_len == 0) {
638 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
640 for (i = 0; i < data->msgout_len; i++) {
648 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
651 msgout |= (unsigned int)data->msgout_len; /* len */
654 /* data->msgout_len > 3 */
669 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
680 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
685 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
692 data->msgout_len, msgout);
697 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
704 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
708 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
710 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
799 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
825 if (newid >= ARRAY_SIZE(data->lunt) || newlun >= ARRAY_SIZE(data->lunt[0])) {
828 } else if(data->lunt[newid][newlun].SCpnt == NULL) {
833 data->cur_id = newid;
834 data->cur_lun = newlun;
835 data->cur_target = &(data->target[newid]);
836 data->cur_lunt = &(data->lunt[newid][newlun]);
846 * nsp32_setup_sg_table - build scatter gather list for transfer data
853 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
855 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
899 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
910 if (data->CurrentSC != NULL) {
912 data->CurrentSC = NULL;
937 data->CurrentSC = SCpnt;
947 /* initialize data */
948 data->msgout_len = 0;
949 data->msgin_len = 0;
950 cur_lunt = &(data->lunt[SCpnt->device->id][SCpnt->device->lun]);
954 data->cur_lunt = cur_lunt;
955 data->cur_id = SCpnt->device->id;
956 data->cur_lun = SCpnt->device->lun;
974 target = &data->target[scmd_id(SCpnt)];
975 data->cur_target = target;
981 nsp32_set_max_sync(data, target, &period, &offset);
985 nsp32_set_async(data, target);
998 nsp32_set_async(data, target);
1010 nsp32_set_async(data, target);
1041 static int nsp32hw_init(nsp32_hw_data *data)
1043 unsigned int base = data->BaseAddress;
1068 if ((data->trans_method & NSP32_TRANSFER_PIO) ||
1069 (data->trans_method & NSP32_TRANSFER_MMIO)) {
1072 } else if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1083 nsp32_index_write1(base, CLOCK_DIV, data->clock);
1150 nsp32_hw_data *data = dev_id;
1151 unsigned int base = data->BaseAddress;
1152 struct scsi_cmnd *SCpnt = data->CurrentSC;
1158 struct Scsi_Host *host = data->Host;
1182 if (data->CurrentSC != NULL) {
1200 nsp32_do_bus_reset(data);
1244 (data->msgout_len <= 3)) {
1249 data->msgout_len = 0;
1277 scsi_set_resid(SCpnt, 0); /* all data transferred! */
1325 nsp32_sack_assert(data);
1326 nsp32_wait_req(data, NEGATE);
1327 nsp32_sack_negate(data);
1435 nsp32_hw_data *data;
1443 data = (nsp32_hw_data *)host->hostdata;
1451 seq_printf(m, "MMIO(virtual address): 0x%lx-0x%lx\n", host->base, host->base + data->MmioLength - 1);
1456 model = data->pci_devid->driver_data;
1463 spin_lock_irqsave(&(data->Lock), flags);
1464 seq_printf(m, "CurrentSC: 0x%p\n\n", data->CurrentSC);
1465 spin_unlock_irqrestore(&(data->Lock), flags);
1469 for (id = 0; id < ARRAY_SIZE(data->target); id++) {
1478 if (data->target[id].sync_flag == SDTR_DONE) {
1479 if (data->target[id].period == 0 &&
1480 data->target[id].offset == ASYNC_OFFSET ) {
1489 if (data->target[id].period != 0) {
1491 speed = 1000000 / (data->target[id].period * 4);
1496 data->target[id].offset
1507 * Reset parameters and call scsi_done for data->cur_lunt.
1512 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1531 data->cur_lunt->SCpnt = NULL;
1532 data->cur_lunt = NULL;
1533 data->cur_target = NULL;
1534 data->CurrentSC = NULL;
1550 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1567 * processing and we can't adjust any SCSI data pointer in next data
1589 * come after data transferring.
1604 data->cur_lunt->msgin03 = FALSE;
1606 data->cur_lunt->msgin03 = TRUE;
1614 //data->cur_lunt->save_datp = data->cur_datp;
1628 if (data->cur_target->sync_flag & SDTR_INITIATOR) {
1633 nsp32_set_async(data, data->cur_target);
1634 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
1635 data->cur_target->sync_flag |= SDTR_DONE;
1636 } else if (data->cur_target->sync_flag & SDTR_TARGET) {
1652 nsp32_set_async(data, data->cur_target);
1654 data->cur_target->sync_flag &= ~SDTR_TARGET;
1655 data->cur_target->sync_flag |= SDTR_DONE;
1708 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1709 int old_entry = data->cur_entry;
1711 int sg_num = data->cur_lunt->sg_num;
1712 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
1755 data->cur_entry = new_entry;
1781 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1788 "enter: msgout_len: 0x%x", data->msgout_len);
1794 if (data->msgout_len == 0) {
1803 new_sgtp = data->cur_lunt->sglun_paddr +
1804 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable));
1809 for (i = 0; i < data->msgout_len; i++) {
1811 "%d : 0x%x", i, data->msgoutbuf[i]);
1816 nsp32_wait_req(data, ASSERT);
1818 if (i == (data->msgout_len - 1)) {
1834 * Write data with SACK, then wait sack is
1837 nsp32_write1(base, SCSI_DATA_WITH_ACK, data->msgoutbuf[i]);
1838 nsp32_wait_sack(data, NEGATE);
1844 data->msgout_len = 0;
1857 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1858 unsigned int base = data->BaseAddress;
1863 if (data->cur_target == NULL || data->cur_lunt == NULL) {
1871 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
1876 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
1881 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
1886 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
1893 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1897 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
1899 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
1925 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1941 data->msginbuf[(unsigned char)data->msgin_len] = msg;
1942 msgtype = data->msginbuf[0];
1945 data->msgin_len, msg, msgtype);
1954 nsp32_sack_assert(data);
2008 data->cur_lunt->msgin03 = FALSE;
2018 new_sgtp = data->cur_lunt->sglun_paddr +
2019 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable));
2037 if (data->cur_target->sync_flag &
2044 nsp32_set_async(data, data->cur_target);
2045 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
2046 data->cur_target->sync_flag |= SDTR_DONE;
2073 if (data->msgin_len >= 1) {
2086 if (data->msgin_len < 1) {
2095 if ((data->msginbuf[1] + 1) > data->msgin_len) {
2110 switch (data->msginbuf[2]) {
2120 if (data->msgin_len != EXTENDED_SDTR_LEN + 1) {
2154 data->msgin_len = 0;
2163 if (data->msgout_len > 0) {
2177 if (data->cur_lunt->msgin03 == TRUE) {
2180 data->cur_lunt->msgin03 = FALSE;
2182 data->msgin_len++;
2193 nsp32_wait_req(data, NEGATE);
2198 nsp32_sack_negate(data);
2208 msg, data->msgin_len, msgtype);
2210 data->msgin_len = 0;
2220 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2221 nsp32_target *target = data->cur_target;
2223 unsigned char get_period = data->msginbuf[3];
2224 unsigned char get_offset = data->msginbuf[4];
2230 synct = data->synct;
2231 syncnum = data->syncnum;
2279 if (get_period < data->synct[0].period_num) {
2287 entry = nsp32_search_period_entry(data, target, get_period);
2300 nsp32_set_sync_entry(data, target, entry, get_offset);
2314 if (get_period < data->synct[0].period_num) {
2315 get_period = data->synct[0].period_num;
2318 entry = nsp32_search_period_entry(data, target, get_period);
2321 nsp32_set_async(data, target);
2324 nsp32_set_sync_entry(data, target, entry, get_offset);
2341 nsp32_set_async(data, target); /* set as ASYNC transfer mode */
2353 static int nsp32_search_period_entry(nsp32_hw_data *data,
2359 if (target->limit_entry >= data->syncnum) {
2364 for (i = target->limit_entry; i < data->syncnum; i++) {
2365 if (period >= data->synct[i].start_period &&
2366 period <= data->synct[i].end_period) {
2375 if (i == data->syncnum) {
2386 static void nsp32_set_async(nsp32_hw_data *data, nsp32_target *target)
2388 unsigned char period = data->synct[target->limit_entry].period_num;
2403 static void nsp32_set_max_sync(nsp32_hw_data *data,
2410 period_num = data->synct[target->limit_entry].period_num;
2411 *period = data->synct[target->limit_entry].start_period;
2412 ackwidth = data->synct[target->limit_entry].ackwidth;
2425 static void nsp32_set_sync_entry(nsp32_hw_data *data,
2432 period = data->synct[entry].period_num;
2433 ackwidth = data->synct[entry].ackwidth;
2434 sample_rate = data->synct[entry].sample_rate;
2453 static void nsp32_wait_req(nsp32_hw_data *data, int state)
2455 unsigned int base = data->BaseAddress;
2482 static void nsp32_wait_sack(nsp32_hw_data *data, int state)
2484 unsigned int base = data->BaseAddress;
2513 static void nsp32_sack_assert(nsp32_hw_data *data)
2515 unsigned int base = data->BaseAddress;
2526 static void nsp32_sack_negate(nsp32_hw_data *data)
2528 unsigned int base = data->BaseAddress;
2549 nsp32_hw_data *data;
2567 data = (nsp32_hw_data *)host->hostdata;
2569 memcpy(data, &nsp32_data_base, sizeof(nsp32_hw_data));
2571 host->irq = data->IrqNumber;
2572 host->io_port = data->BaseAddress;
2573 host->unique_id = data->BaseAddress;
2574 host->n_io_port = data->NumAddress;
2575 host->base = (unsigned long)data->MmioAddress;
2577 data->Host = host;
2578 spin_lock_init(&(data->Lock));
2580 data->cur_lunt = NULL;
2581 data->cur_target = NULL;
2586 data->trans_method = NSP32_TRANSFER_BUSMASTER;
2593 data->clock = CLOCK_4;
2598 switch (data->clock) {
2600 /* If data->clock is CLOCK_4, then select 40M sync table. */
2601 data->synct = nsp32_sync_table_40M;
2602 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2605 /* If data->clock is CLOCK_2, then select 20M sync table. */
2606 data->synct = nsp32_sync_table_20M;
2607 data->syncnum = ARRAY_SIZE(nsp32_sync_table_20M);
2610 /* If data->clock is PCICLK, then select pci sync table. */
2611 data->synct = nsp32_sync_table_pci;
2612 data->syncnum = ARRAY_SIZE(nsp32_sync_table_pci);
2618 data->clock = CLOCK_4;
2619 data->synct = nsp32_sync_table_40M;
2620 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2638 data->autoparam = dma_alloc_coherent(&pdev->dev,
2639 sizeof(nsp32_autoparam), &(data->auto_paddr),
2641 if (data->autoparam == NULL) {
2649 data->sg_list = dma_alloc_coherent(&pdev->dev, NSP32_SG_TABLE_SIZE,
2650 &data->sg_paddr, GFP_KERNEL);
2651 if (data->sg_list == NULL) {
2656 for (i = 0; i < ARRAY_SIZE(data->lunt); i++) {
2657 for (j = 0; j < ARRAY_SIZE(data->lunt[0]); j++) {
2658 int offset = i * ARRAY_SIZE(data->lunt[0]) + j;
2665 .sglun = &(data->sg_list[offset]),
2666 .sglun_paddr = data->sg_paddr + (offset * sizeof(nsp32_sglun)),
2669 data->lunt[i][j] = tmp;
2676 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2677 nsp32_target *target = &(data->target[i]);
2681 nsp32_set_async(data, target);
2687 ret = nsp32_getprom_param(data);
2689 data->resettime = 3; /* default 3 */
2695 nsp32hw_init(data);
2697 snprintf(data->info_str, sizeof(data->info_str),
2719 nsp32_do_bus_reset(data);
2721 ret = request_irq(host->irq, do_nsp32_isr, IRQF_SHARED, "nsp32", data);
2735 data->BaseAddress, data->NumAddress);
2752 free_irq(host->irq, data);
2756 data->sg_list, data->sg_paddr);
2760 data->autoparam, data->auto_paddr);
2771 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2773 if (data->autoparam) {
2774 dma_free_coherent(&data->Pci->dev, sizeof(nsp32_autoparam),
2775 data->autoparam, data->auto_paddr);
2778 if (data->sg_list) {
2779 dma_free_coherent(&data->Pci->dev, NSP32_SG_TABLE_SIZE,
2780 data->sg_list, data->sg_paddr);
2784 free_irq(host->irq, data);
2791 if (data->MmioAddress) {
2792 iounmap(data->MmioAddress);
2800 nsp32_hw_data *data = (nsp32_hw_data *)shpnt->hostdata;
2802 return data->info_str;
2811 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2816 if (data->cur_lunt->SCpnt == NULL) {
2821 if (data->cur_target->sync_flag & (SDTR_INITIATOR | SDTR_TARGET)) {
2823 data->cur_target->sync_flag = 0;
2824 nsp32_set_async(data, data->cur_target);
2837 static void nsp32_do_bus_reset(nsp32_hw_data *data)
2839 unsigned int base = data->BaseAddress;
2858 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2859 nsp32_target *target = &data->target[i];
2862 nsp32_set_async(data, target);
2876 data->CurrentSC = NULL;
2883 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2890 nsp32hw_init(data);
2892 nsp32_do_bus_reset(data);
2907 static int nsp32_getprom_param(nsp32_hw_data *data)
2909 int vendor = data->pci_devid->vendor;
2910 int device = data->pci_devid->device;
2916 ret = nsp32_prom_read(data, 0x7e);
2921 ret = nsp32_prom_read(data, 0x7f);
2932 ret = nsp32_getprom_c16(data);
2935 ret = nsp32_getprom_at24(data);
2938 ret = nsp32_getprom_at24(data);
2944 /* for debug : SPROM data full checking */
2946 val = nsp32_prom_read(data, i);
2956 * AT24C01A (Logitec: LHA-600S), AT24C02 (Melco Buffalo: IFC-USLP) data map:
2982 static int nsp32_getprom_at24(nsp32_hw_data *data)
2994 data->resettime = nsp32_prom_read(data, 0x12);
3009 ret = nsp32_prom_read(data, 0x07);
3031 target = &data->target[i];
3035 ret = nsp32_prom_read(data, i);
3036 entry = nsp32_search_period_entry(data, target, ret);
3050 * C16 110 (I-O Data: SC-NBD) data map:
3069 static int nsp32_getprom_c16(nsp32_hw_data *data)
3080 data->resettime = nsp32_prom_read(data, 0x11);
3086 target = &data->target[i];
3087 ret = nsp32_prom_read(data, i);
3105 entry = nsp32_search_period_entry(data, target, val);
3120 static int nsp32_prom_read(nsp32_hw_data *data, int romaddr)
3125 nsp32_prom_start(data);
3128 nsp32_prom_write_bit(data, 1); /* 1 */
3129 nsp32_prom_write_bit(data, 0); /* 0 */
3130 nsp32_prom_write_bit(data, 1); /* 1 */
3131 nsp32_prom_write_bit(data, 0); /* 0 */
3132 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */
3133 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */
3134 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */
3137 nsp32_prom_write_bit(data, 0);
3140 nsp32_prom_write_bit(data, 0);
3144 nsp32_prom_write_bit(data, ((romaddr >> i) & 1));
3148 nsp32_prom_write_bit(data, 0);
3151 nsp32_prom_start(data);
3154 nsp32_prom_write_bit(data, 1); /* 1 */
3155 nsp32_prom_write_bit(data, 0); /* 0 */
3156 nsp32_prom_write_bit(data, 1); /* 1 */
3157 nsp32_prom_write_bit(data, 0); /* 0 */
3158 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */
3159 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */
3160 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */
3163 nsp32_prom_write_bit(data, 1);
3166 nsp32_prom_write_bit(data, 0);
3168 /* data... */
3171 val += (nsp32_prom_read_bit(data) << i);
3175 nsp32_prom_write_bit(data, 1);
3178 nsp32_prom_stop(data);
3183 static void nsp32_prom_set(nsp32_hw_data *data, int bit, int val)
3185 int base = data->BaseAddress;
3201 static int nsp32_prom_get(nsp32_hw_data *data, int bit)
3203 int base = data->BaseAddress;
3225 static void nsp32_prom_start (nsp32_hw_data *data)
3228 nsp32_prom_set(data, SCL, 1);
3229 nsp32_prom_set(data, SDA, 1);
3230 nsp32_prom_set(data, ENA, 1); /* output mode */
3231 nsp32_prom_set(data, SDA, 0); /* keeping SCL=1 and transiting
3233 nsp32_prom_set(data, SCL, 0);
3236 static void nsp32_prom_stop (nsp32_hw_data *data)
3239 nsp32_prom_set(data, SCL, 1);
3240 nsp32_prom_set(data, SDA, 0);
3241 nsp32_prom_set(data, ENA, 1); /* output mode */
3242 nsp32_prom_set(data, SDA, 1);
3243 nsp32_prom_set(data, SCL, 0);
3246 static void nsp32_prom_write_bit(nsp32_hw_data *data, int val)
3249 nsp32_prom_set(data, SDA, val);
3250 nsp32_prom_set(data, SCL, 1 );
3251 nsp32_prom_set(data, SCL, 0 );
3254 static int nsp32_prom_read_bit(nsp32_hw_data *data)
3259 nsp32_prom_set(data, ENA, 0); /* input mode */
3260 nsp32_prom_set(data, SCL, 1);
3262 val = nsp32_prom_get(data, SDA);
3264 nsp32_prom_set(data, SCL, 0);
3265 nsp32_prom_set(data, ENA, 1); /* output mode */
3294 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
3303 reg = nsp32_read2(data->BaseAddress, INDEX_REG);
3305 nsp32_msg(KERN_INFO, "io=0x%x reg=0x%x", data->BaseAddress, reg);
3312 nsp32hw_init (data);
3313 nsp32_do_bus_reset(data);
3328 nsp32_hw_data *data = &nsp32_data_base;
3338 data->Pci = pdev;
3339 data->pci_devid = id;
3340 data->IrqNumber = pdev->irq;
3341 data->BaseAddress = pci_resource_start(pdev, 0);
3342 data->NumAddress = pci_resource_len (pdev, 0);
3343 data->MmioAddress = pci_ioremap_bar(pdev, 1);
3344 data->MmioLength = pci_resource_len (pdev, 1);
3352 data->MmioAddress, data->MmioLength,