Lines Matching defs:NSP32_DEBUG_INTR
293 #define NSP32_DEBUG_INTR BIT(3)
428 nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time);
431 nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow");
1166 nsp32_dbg(NSP32_DEBUG_INTR,
1170 nsp32_dbg(NSP32_DEBUG_INTR, "shared interrupt: irq other 0x%x", irq_stat);
1192 nsp32_dbg(NSP32_DEBUG_INTR, "timer stop");
1227 nsp32_dbg(NSP32_DEBUG_INTR,
1252 nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed");
1264 nsp32_dbg(NSP32_DEBUG_INTR,
1268 nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx",
1270 nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx",
1272 nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx",
1274 nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx",
1333 nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed");
1345 nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ");
1349 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write");
1356 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read");
1363 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status");
1369 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase");
1370 nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1380 nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ");
1384 nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in");
1399 nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred");
1414 nsp32_dbg(NSP32_DEBUG_INTR,
1426 nsp32_dbg(NSP32_DEBUG_INTR, "exit");