Lines Matching refs:mvi
12 static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
23 void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
25 void *bitmap = mvi->tags;
29 void mvs_tag_free(struct mvs_info *mvi, u32 tag)
31 mvs_tag_clear(mvi, tag);
34 void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
36 void *bitmap = mvi->tags;
40 inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
43 void *bitmap = mvi->tags;
45 index = find_first_zero_bit(bitmap, mvi->tags_num);
47 if (tag >= mvi->tags_num)
49 mvs_tag_set(mvi, tag);
54 void mvs_tag_init(struct mvs_info *mvi)
57 for (i = 0; i < mvi->tags_num; ++i)
58 mvs_tag_clear(mvi, i);
65 struct mvs_info *mvi = NULL;
83 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
85 return mvi;
93 struct mvs_info *mvi = mvi_dev->mvi_info;
107 phyno[n] = (j >= mvi->chip->n_phy) ?
108 (j - mvi->chip->n_phy) : j;
119 struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi,
124 if (mvi->devices[dev_no].taskfileset == MVS_ID_NOT_MAPPED)
127 if (mvi->devices[dev_no].taskfileset == reg_set)
128 return &mvi->devices[dev_no];
133 static inline void mvs_free_reg_set(struct mvs_info *mvi,
142 MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
145 static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
150 return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
153 void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
159 MVS_CHIP_DISP->phy_reset(mvi, no, hard);
169 struct mvs_info *mvi = NULL;
177 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
181 MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
185 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
188 MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET);
192 MVS_CHIP_DISP->phy_enable(mvi, phy_id);
193 MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET);
197 MVS_CHIP_DISP->phy_disable(mvi, phy_id);
207 void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
213 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
214 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
215 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
216 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
219 static void mvs_bytes_dmaed(struct mvs_info *mvi, int i, gfp_t gfp_flags)
221 struct mvs_phy *phy = &mvi->phy[i];
254 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
255 MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x00);
260 mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
271 struct mvs_info *mvi;
278 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
279 for (i = 0; i < mvi->chip->n_phy; ++i)
280 mvs_bytes_dmaed(mvi, i, GFP_KERNEL);
297 static int mvs_task_prep_smp(struct mvs_info *mvi,
301 struct sas_ha_struct *sha = mvi->sas;
314 struct mvs_slot_info *slot = &mvi->slot_info[tag];
321 elem = dma_map_sg(mvi->dev, sg_req, 1, DMA_TO_DEVICE);
327 elem = dma_map_sg(mvi->dev, sg_resp, 1, DMA_FROM_DEVICE);
371 if (mvi->flags & MVF_FLAG_SOC)
377 slot->tx = mvi->tx_prod;
378 mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
400 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
403 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
426 static int mvs_task_prep_ata(struct mvs_info *mvi,
444 if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
449 slot = &mvi->slot_info[tag];
450 slot->tx = mvi->tx_prod;
455 mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
516 if (mvi->flags & MVF_FLAG_SOC)
546 MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask,
552 static int mvs_task_prep_ssp(struct mvs_info *mvi,
573 slot = &mvi->slot_info[tag];
578 slot->tx = mvi->tx_prod;
579 mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
631 if (mvi->flags & MVF_FLAG_SOC)
693 static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
752 n_elem = dma_map_sg(mvi->dev,
765 rc = mvs_tag_alloc(mvi, &tag);
769 slot = &mvi->slot_info[tag];
775 slot->buf = dma_pool_zalloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
782 tei.hdr = &mvi->slot[tag];
787 rc = mvs_task_prep_smp(mvi, &tei);
790 rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
795 rc = mvs_task_prep_ata(mvi, &tei);
798 dev_printk(KERN_ERR, mvi->dev,
819 mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
824 dma_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
826 mvs_tag_free(mvi, tag);
829 dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
832 dma_unmap_sg(mvi->dev, task->scatter, n_elem,
842 struct mvs_info *mvi = NULL;
847 mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
849 spin_lock_irqsave(&mvi->lock, flags);
850 rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
852 dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
855 MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
857 spin_unlock_irqrestore(&mvi->lock, flags);
867 static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
870 mvs_tag_clear(mvi, slot_idx);
873 static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
882 dma_unmap_sg(mvi->dev, task->scatter,
887 dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
889 dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
902 dma_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
910 mvs_slot_free(mvi, slot_idx);
913 static void mvs_update_wideport(struct mvs_info *mvi, int phy_no)
915 struct mvs_phy *phy = &mvi->phy[phy_no];
921 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
923 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
926 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
928 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
934 static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
937 struct mvs_phy *phy = &mvi->phy[i];
940 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
952 mvs_update_wideport(mvi, i);
962 static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
969 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
970 s[3] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
972 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
973 s[2] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
975 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
976 s[1] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
978 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
979 s[0] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
999 void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
1001 struct mvs_phy *phy = &mvi->phy[i];
1007 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
1008 phy->phy_status = mvs_is_phy_ready(mvi, i);
1013 struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
1015 oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
1017 MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
1024 i + mvi->id * mvi->chip->n_phy;
1029 mvs_get_d2h_reg(mvi, i, id);
1032 dev_printk(KERN_DEBUG, mvi->dev,
1034 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
1035 MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
1062 MVS_CHIP_DISP->phy_work_around(mvi, i);
1065 i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
1067 i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
1070 MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
1076 struct mvs_info *mvi = NULL; int i = 0, hi;
1090 mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
1091 if (i >= mvi->chip->n_phy)
1092 port = &mvi->port[i - mvi->chip->n_phy];
1094 port = &mvi->port[i];
1096 spin_lock_irqsave(&mvi->lock, flags);
1103 mvs_update_wideport(mvi, sas_phy->id);
1107 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
1108 MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x04);
1112 spin_unlock_irqrestore(&mvi->lock, flags);
1119 struct mvs_info *mvi = phy->mvi;
1123 while (phy != &mvi->phy[phy_no]) {
1129 mvs_do_release_task(phy->mvi, phy_no, dev);
1144 static struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
1148 if (mvi->devices[dev].dev_type == SAS_PHY_UNUSED) {
1149 mvi->devices[dev].device_id = dev;
1150 return &mvi->devices[dev];
1175 struct mvs_info *mvi = NULL;
1179 mvi = mvs_find_dev_mvi(dev);
1182 spin_lock_irqsave(&mvi->lock, flags);
1184 mvi_device = mvs_alloc_dev(mvi);
1192 mvi_device->mvi_info = mvi;
1218 spin_unlock_irqrestore(&mvi->lock, flags);
1231 struct mvs_info *mvi;
1238 mvi = mvi_dev->mvi_info;
1240 spin_lock_irqsave(&mvi->lock, flags);
1244 mvs_release_task(mvi, dev);
1245 mvs_free_reg_set(mvi, mvi_dev);
1251 spin_unlock_irqrestore(&mvi->lock, flags);
1387 struct mvs_info *mvi = mvi_dev->mvi_info;
1393 spin_lock_irqsave(&mvi->lock, flags);
1394 mvs_release_task(mvi, dev);
1395 spin_unlock_irqrestore(&mvi->lock, flags);
1408 struct mvs_info *mvi = mvi_dev->mvi_info;
1418 spin_lock_irqsave(&mvi->lock, flags);
1419 mvs_release_task(mvi, dev);
1420 spin_unlock_irqrestore(&mvi->lock, flags);
1436 struct mvs_info *mvi = mvi_dev->mvi_info;
1439 rc = mvs_find_tag(mvi, task, &tag);
1469 struct mvs_info *mvi;
1479 mvi = mvi_dev->mvi_info;
1493 rc = mvs_find_tag(mvi, task, &tag);
1512 slot_no = (u32) (slot - mvi->slot_info);
1513 spin_lock_irqsave(&mvi->lock, flags);
1514 mvs_slot_complete(mvi, slot_no, 1);
1515 spin_unlock_irqrestore(&mvi->lock, flags);
1523 u32 slot_idx = (u32)(slot - mvi->slot_info);
1524 mv_dprintk("mvs_abort_task() mvi=%p task=%p "
1526 mvi, task, slot, slot_idx);
1528 mvs_slot_task_free(mvi, task, slot, slot_idx);
1573 static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
1647 static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
1650 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1658 MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
1660 MVS_CHIP_DISP->command_active(mvi, slot_idx);
1671 sas_ssp_task_response(mvi->dev, task, iu);
1688 mvs_sata_done(mvi, task, slot_idx, err_dw0);
1698 int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
1701 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1734 mvs_free_reg_set(mvi, mvi_dev);
1736 mvs_slot_task_free(mvi, task, slot, slot_idx);
1758 tstat->stat = mvs_slot_err(mvi, task, slot_idx);
1774 sas_ssp_task_response(mvi->dev, task, iu);
1793 tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
1811 mvs_free_reg_set(mvi, mvi_dev);
1813 mvs_slot_task_free(mvi, task, slot, slot_idx);
1816 spin_unlock(&mvi->lock);
1820 spin_lock(&mvi->lock);
1825 void mvs_do_release_task(struct mvs_info *mvi,
1833 phy = &mvi->phy[phy_no];
1838 mvs_int_rx(mvi, false);
1844 slot_idx = (u32) (slot - mvi->slot_info);
1852 MVS_CHIP_DISP->command_active(mvi, slot_idx);
1854 mvs_slot_complete(mvi, slot_idx, 1);
1858 void mvs_release_task(struct mvs_info *mvi,
1864 mvs_do_release_task(mvi, phyno[i], dev);
1878 struct mvs_info *mvi = mwq->mvi;
1881 struct mvs_phy *phy = &mvi->phy[phy_no];
1884 spin_lock_irqsave(&mvi->lock, flags);
1890 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
1899 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
1900 mvs_update_phyinfo(mvi, phy_no, 1);
1901 mvs_bytes_dmaed(mvi, phy_no, GFP_ATOMIC);
1913 spin_unlock_irqrestore(&mvi->lock, flags);
1917 static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
1924 mwq->mvi = mvi;
1928 list_add_tail(&mwq->entry, &mvi->wq_list);
1939 struct mvs_info *mvi = phy->mvi;
1942 for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
1943 if (&mvi->phy[phy_no] == phy) {
1945 phy_no+mvi->id*mvi->chip->n_phy);
1946 MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET);
1951 void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
1954 struct mvs_phy *phy = &mvi->phy[phy_no];
1956 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
1957 MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
1958 mv_dprintk("phy %d ctrl sts=0x%08X.\n", phy_no+mvi->id*mvi->chip->n_phy,
1959 MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
1960 mv_dprintk("phy %d irq sts = 0x%08X\n", phy_no+mvi->id*mvi->chip->n_phy,
1970 phy_no + mvi->id*mvi->chip->n_phy);
1978 mvs_do_release_task(mvi, phy_no, NULL);
1980 MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
1981 mvs_handle_event(mvi,
1984 ready = mvs_is_phy_ready(mvi, phy_no);
1987 MVS_CHIP_DISP->stp_reset(mvi,
1990 MVS_CHIP_DISP->phy_reset(mvi,
1998 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
1999 MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
2008 phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
2012 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
2015 mvi, phy_no);
2017 MVS_CHIP_DISP->write_port_irq_mask(mvi,
2020 mvs_update_phyinfo(mvi, phy_no, 0);
2022 MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE);
2026 mvs_bytes_dmaed(mvi, phy_no, GFP_ATOMIC);
2034 phy_no + mvi->id*mvi->chip->n_phy);
2038 phy_no + mvi->id*mvi->chip->n_phy);
2039 mvs_handle_event(mvi, (void *)(unsigned long)phy_no,
2044 int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
2054 rx_prod_idx = mvi->rx_cons;
2055 mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
2056 if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
2063 if (unlikely(mvi->rx_cons == rx_prod_idx))
2064 mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
2066 if (mvi->rx_cons == rx_prod_idx)
2069 while (mvi->rx_cons != rx_prod_idx) {
2072 rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
2075 mvs_slot_complete(mvi, rx_desc, 0);
2080 mvs_slot_complete(mvi, rx_desc, 0);
2082 mvs_slot_free(mvi, rx_desc);
2087 MVS_CHIP_DISP->int_full(mvi);
2095 struct mvs_info *mvi = mvs_prv->mvi[0];