Lines Matching refs:port
42 static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
45 return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) :
46 mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4);
49 static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
52 if (port < 4)
53 mw32(MVS_P0_SER_CTLSTAT + port * 4, val);
55 mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val);
59 u32 off2, u32 port)
63 return (port < 4) ? readl(regs + port * 8) :
64 readl(regs2 + (port - 4) * 8);
68 u32 port, u32 val)
72 if (port < 4)
73 writel(val, regs + port * 8);
75 writel(val, regs2 + (port - 4) * 8);
78 static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
81 MVS_P4_CFG_DATA, port);
85 u32 port, u32 val)
88 MVS_P4_CFG_DATA, port, val);
92 u32 port, u32 addr)
95 MVS_P4_CFG_ADDR, port, addr);
99 static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
102 MVS_P4_VSR_DATA, port);
106 u32 port, u32 val)
109 MVS_P4_VSR_DATA, port, val);
113 u32 port, u32 addr)
116 MVS_P4_VSR_ADDR, port, addr);
120 static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
123 MVS_P4_INT_STAT, port);
127 u32 port, u32 val)
130 MVS_P4_INT_STAT, port, val);
133 static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
136 MVS_P4_INT_MASK, port);
141 u32 port, u32 val)
144 MVS_P4_INT_MASK, port, val);
167 /* not to halt for different port op during wideport link change */