Lines Matching refs:phy_cfg
166 union reg_phy_cfg phy_cfg, phy_cfg_tmp;
169 phy_cfg.v = 0;
170 phy_cfg.u.disable_phy = phy_cfg_tmp.u.disable_phy;
171 phy_cfg.u.sas_support = 1;
172 phy_cfg.u.sata_support = 1;
173 phy_cfg.u.sata_host_mode = 1;
178 phy_cfg.u.speed_support = 1;
179 phy_cfg.u.snw_3_support = 0;
180 phy_cfg.u.tx_lnk_parity = 1;
181 phy_cfg.u.tx_spt_phs_lnk_rate = 0x30;
186 phy_cfg.u.speed_support = 3;
187 phy_cfg.u.tx_spt_phs_lnk_rate = 0x3c;
188 phy_cfg.u.tx_lgcl_lnk_rate = 0x08;
193 phy_cfg.u.speed_support = 7;
194 phy_cfg.u.snw_3_support = 1;
195 phy_cfg.u.tx_lnk_parity = 1;
196 phy_cfg.u.tx_spt_phs_lnk_rate = 0x3f;
197 phy_cfg.u.tx_lgcl_lnk_rate = 0x09;
200 mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v);