Lines Matching refs:mw32
38 mw32(MVS_PCS, tmp);
55 mw32(MVS_GBL_PORT_TYPE, 0);
98 mw32(MVS_PHY_CTL, tmp);
100 mw32(MVS_PHY_CTL, reg);
132 mw32(MVS_INT_STAT_SRS_0, tmp);
139 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));
151 mw32(MVS_GBL_CTL, 0);
170 mw32(MVS_GBL_CTL, 0);
212 mw32(MVS_PHY_CTL, tmp);
234 mw32(MVS_PHY_CTL, tmp);
255 mw32(MVS_PHY_CTL, tmp);
288 mw32(MVS_PHY_CTL, tmp);
291 mw32(MVS_PHY_CTL, tmp);
296 mw32(MVS_PCS, 0); /* MVS_PCS */
306 mw32(MVS_GBL_PORT_TYPE, MODE_AUTO_DET_EN);
308 mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
309 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
311 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
312 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
314 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);
315 mw32(MVS_TX_LO, mvi->tx_dma);
316 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
318 mw32(MVS_RX_CFG, MVS_RX_RING_SZ);
319 mw32(MVS_RX_LO, mvi->rx_dma);
320 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
373 mw32(MVS_PCS, tmp);
380 mw32(MVS_INT_COAL, 0x1ff | COAL_EN);
382 mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ | COAL_EN);
385 mw32(MVS_INT_COAL_TMOUT, tmp);
388 mw32(MVS_TX_CFG, 0);
389 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
390 mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);
392 mw32(MVS_PCS, PCS_SATA_RETRY | PCS_FIS_RX_EN |
399 mw32(MVS_INT_MASK, tmp);
402 mw32(MVS_INT_MASK_SRS_0, 0xFFFF);
426 mw32(MVS_GBL_CTL, tmp | INT_EN);
435 mw32(MVS_GBL_CTL, tmp & ~INT_EN);
488 mw32(MVS_INT_STAT_SRS_0, tmp);
490 mw32(MVS_INT_STAT, CINT_CI_STOP);
492 mw32(MVS_PCS, tmp);
506 mw32(MVS_PCS, tmp & ~offs);
509 mw32(MVS_CTL, tmp & ~offs);
514 mw32(MVS_INT_STAT_SRS_0, tmp);
539 mw32(MVS_PCS, tmp | offs);
541 mw32(MVS_CTL, tmp | offs);
544 mw32(MVS_INT_STAT_SRS_0, tmp);
648 mw32(MVS_PCS, tmp & 0xFFFF);
649 mw32(MVS_PCS, tmp);
651 mw32(MVS_CTL, tmp & 0xFFFF);
652 mw32(MVS_CTL, tmp);
748 mw32(MVS_INT_COAL, 0);
749 mw32(MVS_INT_COAL_TMOUT, 0x10000);
752 mw32(MVS_INT_COAL, 0x1ff|COAL_EN);
754 mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ|COAL_EN);
757 mw32(MVS_INT_COAL_TMOUT, tmp);