Lines Matching refs:mr
305 volatile struct mesh_regs __iomem *mr = ms->mesh;
311 ms, mr, md);
314 (mr->count_hi << 8) + mr->count_lo, mr->sequence,
315 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
316 mr->exception, mr->error, mr->intr_mask, mr->interrupt,
317 mr->sync_params);
318 while(in_8(&mr->fifo_count))
319 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
339 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr)
341 (void)in_8(&mr->mesh_id);
360 volatile struct mesh_regs __iomem *mr = ms->mesh;
363 mesh_flush_io(mr);
368 out_8(&mr->exception, 0xff); /* clear all exception bits */
369 out_8(&mr->error, 0xff); /* clear all error bits */
370 out_8(&mr->sequence, SEQ_RESETMESH);
371 mesh_flush_io(mr);
373 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
374 out_8(&mr->source_id, ms->host->this_id);
375 out_8(&mr->sel_timeout, 25); /* 250ms */
376 out_8(&mr->sync_params, ASYNC_PARAMS);
382 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
383 mesh_flush_io(mr);
385 out_8(&mr->bus_status1, 0); /* negate RST */
386 mesh_flush_io(mr);
393 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */
394 out_8(&mr->sequence, SEQ_FLUSHFIFO);
395 mesh_flush_io(mr);
397 out_8(&mr->sync_params, ASYNC_PARAMS);
398 out_8(&mr->sequence, SEQ_ENBRESEL);
407 volatile struct mesh_regs __iomem *mr = ms->mesh;
446 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
447 out_8(&mr->interrupt, INT_CMDDONE);
448 out_8(&mr->sequence, SEQ_ENBRESEL);
449 mesh_flush_io(mr);
452 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
458 MKWORD(mr->interrupt, mr->exception,
459 mr->error, mr->fifo_count));
461 if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0)
463 if (in_8(&mr->interrupt) != 0) {
465 MKWORD(mr->interrupt, mr->exception,
466 mr->error, mr->fifo_count));
473 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
486 out_8(&mr->dest_id, mr->source_id);
500 out_8(&mr->sequence, SEQ_DISRESEL);
501 if (in_8(&mr->interrupt) != 0) {
503 MKWORD(mr->interrupt, mr->exception,
504 mr->error, mr->fifo_count));
509 MKWORD(mr->interrupt, mr->exception,
510 mr->error, mr->fifo_count));
513 out_8(&mr->sequence, SEQ_ARBITRATE);
516 if (in_8(&mr->interrupt) != 0)
521 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
522 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
523 && (in_8(&mr->bus_status0) & BS0_IO)) {
526 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
527 out_8(&mr->sequence, SEQ_RESETMESH);
528 mesh_flush_io(mr);
530 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
531 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
532 out_8(&mr->sequence, SEQ_ENBRESEL);
533 mesh_flush_io(mr);
534 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t)
537 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
539 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
540 && (in_8(&mr->bus_status0) & BS0_IO)) {
641 volatile struct mesh_regs __iomem *mr = ms->mesh;
651 out_8(&mr->sync_params, ASYNC_PARAMS);
674 out_8(&mr->sync_params, tp->sync_params);
682 volatile struct mesh_regs __iomem *mr = ms->mesh;
688 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
689 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
696 out_8(&mr->count_hi, 0);
697 out_8(&mr->count_lo, 1);
698 out_8(&mr->sequence, SEQ_MSGIN + seq);
724 out_8(&mr->count_hi, 0);
725 out_8(&mr->sequence, SEQ_FLUSHFIFO);
726 mesh_flush_io(mr);
732 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) {
733 dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0);
734 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
735 mesh_flush_io(mr);
737 out_8(&mr->count_lo, 1);
738 out_8(&mr->sequence, SEQ_MSGOUT + seq);
739 out_8(&mr->bus_status0, 0); /* release explicit ATN */
740 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
751 out_8(&mr->count_lo, ms->n_msgout - 1);
752 out_8(&mr->sequence, SEQ_MSGOUT + seq);
754 out_8(&mr->fifo, ms->msgout[i]);
765 out_8(&mr->dest_id, ms->conn_tgt);
766 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
769 out_8(&mr->sync_params, tp->sync_params);
770 out_8(&mr->count_hi, 0);
772 out_8(&mr->count_lo, cmd->cmd_len);
773 out_8(&mr->sequence, SEQ_COMMAND + seq);
775 out_8(&mr->fifo, cmd->cmnd[i]);
777 out_8(&mr->count_lo, 6);
778 out_8(&mr->sequence, SEQ_COMMAND + seq);
780 out_8(&mr->fifo, 0);
796 out_8(&mr->count_lo, nb);
797 out_8(&mr->count_hi, nb >> 8);
798 out_8(&mr->sequence, (tp->data_goes_out?
802 out_8(&mr->count_hi, 0);
803 out_8(&mr->count_lo, 1);
804 out_8(&mr->sequence, SEQ_STATUS + seq);
808 out_8(&mr->sequence, SEQ_ENBRESEL);
809 mesh_flush_io(mr);
812 MKWORD(mr->interrupt, mr->exception, mr->error,
813 mr->fifo_count));
814 out_8(&mr->sequence, SEQ_BUSFREE);
826 volatile struct mesh_regs __iomem *mr = ms->mesh;
829 n = mr->fifo_count;
834 ms->msgin[i++] = in_8(&mr->fifo);
858 volatile struct mesh_regs __iomem *mr = ms->mesh;
904 while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) {
907 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
908 mesh_flush_io(mr);
910 out_8(&mr->sequence, SEQ_ENBRESEL);
911 mesh_flush_io(mr);
914 MKWORD(0, mr->error, mr->exception, mr->fifo_count));
916 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
917 mesh_flush_io(mr);
919 out_8(&mr->sequence, SEQ_ENBRESEL);
920 mesh_flush_io(mr);
922 out_8(&mr->sync_params, ASYNC_PARAMS);
927 if (in_8(&mr->fifo_count) == 0) {
934 b = in_8(&mr->fifo);
936 } while (in_8(&mr->fifo_count));
952 out_8(&mr->sync_params, tp->sync_params);
965 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
991 volatile struct mesh_regs __iomem *mr = ms->mesh;
1011 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1012 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1013 mesh_flush_io(mr);
1015 out_8(&mr->sync_params, ASYNC_PARAMS);
1016 out_8(&mr->sequence, SEQ_ENBRESEL);
1034 volatile struct mesh_regs __iomem *mr = ms->mesh;
1036 err = in_8(&mr->error);
1037 exc = in_8(&mr->exception);
1038 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1040 MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1045 while ((in_8(&mr->bus_status1) & BS1_RST) != 0)
1066 out_8(&mr->interrupt, INT_CMDDONE);
1086 count = (mr->count_hi << 8) + mr->count_lo;
1091 out_8(&mr->sequence, mr->sequence);
1117 if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) {
1130 volatile struct mesh_regs __iomem *mr = ms->mesh;
1132 exc = in_8(&mr->exception);
1133 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1324 volatile struct mesh_regs __iomem *mr = ms->mesh;
1331 while (t > 0 && in_8(&mr->fifo_count) != 0
1338 nb = (mr->count_hi << 8) + mr->count_lo;
1340 MKWORD(0, mr->fifo_count, 0, nb));
1342 nb += mr->fifo_count;
1369 volatile struct mesh_regs __iomem *mr = ms->mesh;
1373 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1374 phase = in_8(&mr->bus_status0) & BS0_PHASE;
1377 out_8(&mr->count_lo, 1);
1378 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1379 mesh_flush_io(mr);
1381 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1394 if (mr->fifo_count) {
1395 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1396 mesh_flush_io(mr);
1448 volatile struct mesh_regs __iomem *mr = ms->mesh;
1453 dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
1467 out_8(&mr->count_lo, n - ms->n_msgin);
1468 out_8(&mr->sequence, SEQ_MSGIN + seq);
1477 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1478 mesh_flush_io(mr);
1480 out_8(&mr->count_lo, 1);
1481 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
1496 out_8(&mr->count_lo, 1);
1497 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
1499 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0)
1502 MKWORD(mr->error, mr->exception,
1503 mr->fifo_count, mr->count_lo));
1504 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1508 if (in_8(&mr->interrupt) & INT_ERROR) {
1510 in_8(&mr->error));
1514 if (in_8(&mr->exception) != EXC_PHASEMM)
1516 in_8(&mr->exception));
1519 in_8(&mr->bus_status0));
1523 if (in_8(&mr->bus_status0) & BS0_REQ) {
1524 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1525 mesh_flush_io(mr);
1527 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1530 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1572 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) {
1596 out_8(&mr->sequence, 0);
1597 out_8(&mr->interrupt,
1603 cmd->SCp.Status = mr->fifo;
1662 volatile struct mesh_regs __iomem *mr = ms->mesh;
1668 "phase=%d msgphase=%d\n", mr->bus_status0,
1669 mr->interrupt, mr->exception, mr->error,
1672 while ((intr = in_8(&mr->interrupt)) != 0) {
1674 MKWORD(intr, mr->error, mr->exception, mr->sequence));
1680 out_8(&mr->interrupt, INT_CMDDONE);
1710 volatile struct mesh_regs __iomem *mr = ms->mesh;
1723 out_8(&mr->exception, 0xff); /* clear all exception bits */
1724 out_8(&mr->error, 0xff); /* clear all error bits */
1725 out_8(&mr->sequence, SEQ_RESETMESH);
1726 mesh_flush_io(mr);
1728 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1729 out_8(&mr->source_id, ms->host->this_id);
1730 out_8(&mr->sel_timeout, 25); /* 250ms */
1731 out_8(&mr->sync_params, ASYNC_PARAMS);
1734 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
1735 mesh_flush_io(mr);
1737 out_8(&mr->bus_status1, 0); /* negate RST */
1821 volatile struct mesh_regs __iomem *mr;
1826 mr = ms->mesh;
1827 out_8(&mr->intr_mask, 0);
1828 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1829 out_8(&mr->bus_status1, BS1_RST);
1830 mesh_flush_io(mr);
1832 out_8(&mr->bus_status1, 0);