Lines Matching refs:mem_ptr
2049 (unsigned long)ha->mem_ptr);
2249 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2253 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2256 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2260 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2264 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2268 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2271 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2274 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2277 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2280 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
4255 if (ha->mem_ptr) {
4258 ha->mem_ptr = NULL;
4501 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4502 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4530 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4531 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4660 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4661 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4679 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4681 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4682 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4799 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4811 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4812 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4825 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4837 readb(ha->mem_ptr + IPS_REG_ISPR);
4838 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4842 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4856 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4859 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4863 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4866 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4894 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4911 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4919 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4922 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4939 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4950 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4967 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
4971 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4974 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4976 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
5058 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5063 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5104 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5175 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5177 ha->mem_ptr + IPS_REG_SQER);
5178 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5179 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5234 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5255 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5345 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5361 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5362 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5426 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5480 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5491 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5513 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
6133 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6137 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6142 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6147 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6152 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6160 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6164 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6178 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6186 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6190 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6214 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6219 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6339 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6343 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6347 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6355 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6359 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6370 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6374 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6384 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6388 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6397 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6401 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6475 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6479 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6482 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6485 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6491 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6496 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6840 char __iomem *mem_ptr;
6884 mem_ptr = ioremap_ptr + offs;
6887 mem_ptr = NULL;
6907 ha->mem_ptr = mem_ptr;
7009 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);