Lines Matching refs:io_addr
2038 if (ha->io_addr)
2041 ha->io_addr, ha->io_len);
2286 outl(0, ha->io_addr + IPS_REG_FLAP);
2290 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2293 outl(1, ha->io_addr + IPS_REG_FLAP);
2297 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2301 outl(0x1FF, ha->io_addr + IPS_REG_FLAP);
2305 major = inb(ha->io_addr + IPS_REG_FLDP);
2308 outl(0x1FE, ha->io_addr + IPS_REG_FLAP);
2312 minor = inb(ha->io_addr + IPS_REG_FLDP);
2315 outl(0x1FD, ha->io_addr + IPS_REG_FLAP);
2319 subminor = inb(ha->io_addr + IPS_REG_FLDP);
4475 isr = inb(ha->io_addr + IPS_REG_HISR);
4476 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4643 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4644 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4706 Isr = inb(ha->io_addr + IPS_REG_HISR);
4718 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4719 outb(Isr, ha->io_addr + IPS_REG_HISR);
4732 Isr = inb(ha->io_addr + IPS_REG_HISR);
4744 inb(ha->io_addr + IPS_REG_ISPR);
4745 outb(Isr, ha->io_addr + IPS_REG_HISR);
4749 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4763 outl(0x1010, ha->io_addr + IPS_REG_CCCR);
4766 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4770 outl(0, ha->io_addr + IPS_REG_NDAE);
4773 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
5006 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
5013 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5018 outb(0, ha->io_addr + IPS_REG_SCPR);
5144 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR);
5146 ha->io_addr + IPS_REG_SQER);
5148 ha->io_addr + IPS_REG_SQHR);
5149 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR);
5207 ha->io_addr + IPS_REG_SQTR);
5292 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5308 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR);
5309 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR);
5394 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ);
5447 Isr = inb(ha->io_addr + IPS_REG_HISR);
5458 outb(Isr, ha->io_addr + IPS_REG_HISR);
6021 outl(0, ha->io_addr + IPS_REG_FLAP);
6025 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6030 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6035 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6040 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6048 outl(0, ha->io_addr + IPS_REG_FLAP);
6052 status = inb(ha->io_addr + IPS_REG_FLDP);
6066 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6074 outl(0, ha->io_addr + IPS_REG_FLAP);
6078 status = inb(ha->io_addr + IPS_REG_FLDP);
6102 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6107 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6248 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6252 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6256 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6264 outl(0, ha->io_addr + IPS_REG_FLAP);
6268 status = inb(ha->io_addr + IPS_REG_FLDP);
6279 outl(0, ha->io_addr + IPS_REG_FLAP);
6283 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6293 outl(0, ha->io_addr + IPS_REG_FLAP);
6297 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6306 outl(0, ha->io_addr + IPS_REG_FLAP);
6310 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6426 outl(0, ha->io_addr + IPS_REG_FLAP);
6430 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6433 outl(1, ha->io_addr + IPS_REG_FLAP);
6436 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6442 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6446 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6674 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
6832 uint32_t io_addr;
6857 io_addr = 0;
6866 io_addr = pci_resource_start(pci_dev, j);
6903 ha->io_addr = io_addr;