Lines Matching defs:base
162 static void initio_se2_ew_en(unsigned long base);
163 static void initio_se2_ew_ds(unsigned long base);
164 static int initio_se2_rd_all(unsigned long base);
165 static void initio_se2_update_all(unsigned long base); /* setup default pattern */
166 static void initio_read_eeprom(unsigned long base);
270 * @base: Base of InitIO controller
276 static void initio_se2_instr(unsigned long base, u8 instr)
281 outb(SE2CS | SE2DO, base + TUL_NVRAM); /* cs+start bit */
283 outb(SE2CS | SE2CLK | SE2DO, base + TUL_NVRAM); /* +CLK */
291 outb(b, base + TUL_NVRAM);
293 outb(b | SE2CLK, base + TUL_NVRAM); /* +CLK */
297 outb(SE2CS, base + TUL_NVRAM); /* -CLK */
304 * @base: Base address of InitIO controller
308 void initio_se2_ew_en(unsigned long base)
310 initio_se2_instr(base, 0x30); /* EWEN */
311 outb(0, base + TUL_NVRAM); /* -CS */
318 * @base: Base address of InitIO controller
322 void initio_se2_ew_ds(unsigned long base)
324 initio_se2_instr(base, 0); /* EWDS */
325 outb(0, base + TUL_NVRAM); /* -CS */
332 * @base: Base of InitIO controller
337 static u16 initio_se2_rd(unsigned long base, u8 addr)
344 initio_se2_instr(base, instr); /* READ INSTR */
347 outb(SE2CS | SE2CLK, base + TUL_NVRAM); /* +CLK */
349 outb(SE2CS, base + TUL_NVRAM); /* -CLK */
352 rb = inb(base + TUL_NVRAM);
358 outb(0, base + TUL_NVRAM); /* no chip select */
365 * @base: Base of InitIO controller
372 static void initio_se2_wr(unsigned long base, u8 addr, u16 val)
379 initio_se2_instr(base, instr); /* WRITE INSTR */
382 outb(SE2CS | SE2DO, base + TUL_NVRAM); /* -CLK+dataBit 1 */
384 outb(SE2CS, base + TUL_NVRAM); /* -CLK+dataBit 0 */
386 outb(SE2CS | SE2CLK, base + TUL_NVRAM); /* +CLK */
390 outb(SE2CS, base + TUL_NVRAM); /* -CLK */
392 outb(0, base + TUL_NVRAM); /* -CS */
395 outb(SE2CS, base + TUL_NVRAM); /* +CS */
399 outb(SE2CS | SE2CLK, base + TUL_NVRAM); /* +CLK */
401 outb(SE2CS, base + TUL_NVRAM); /* -CLK */
403 if ((rb = inb(base + TUL_NVRAM)) & SE2DI)
406 outb(0, base + TUL_NVRAM); /* -CS */
411 * @base: Base address of InitIO controller
417 static int initio_se2_rd_all(unsigned long base)
426 *np++ = initio_se2_rd(base, i);
442 * @base: Base of InitIO controller
447 static void initio_se2_update_all(unsigned long base)
459 initio_se2_ew_en(base); /* Enable write */
465 initio_se2_wr(base, i, *np);
467 initio_se2_ew_ds(base); /* Disable write */
472 * @base: Base of InitIO Host Adapter
483 static void initio_read_eeprom(unsigned long base)
489 gctrl = inb(base + TUL_GCTRL);
490 outb(gctrl | TUL_GCTRL_EEPROM_BIT, base + TUL_GCTRL);
491 if (initio_se2_rd_all(base) != 1) {
492 initio_se2_update_all(base); /* setup default pattern */
493 initio_se2_rd_all(base); /* load again */
496 gctrl = inb(base + TUL_GCTRL);
497 outb(gctrl & ~TUL_GCTRL_EEPROM_BIT, base + TUL_GCTRL);
2899 shost->base = host->addr;