Lines Matching defs:queue
1066 * Tell the controller to post the reply to the queue for this
1087 /* Tell the controller to post the reply to the queue for this
1106 * Tell the controller to post the reply to the queue for this
4179 /* get physical drive ioaccel handle and queue depth */
5061 /* Try to honor the device's queue depth */
5894 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5978 * If no specific reply queue was requested, then send the TUR
5979 * repeatedly, requesting a reply on each reply queue; otherwise execute
5980 * the loop exactly once using only the specified queue.
6981 static struct ctlr_info *queue_to_hba(u8 *queue)
6983 return container_of((queue - *queue), struct ctlr_info, q[0]);
6986 static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6988 struct ctlr_info *h = queue_to_hba(queue);
6989 u8 q = *(u8 *) queue;
7006 static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
7008 struct ctlr_info *h = queue_to_hba(queue);
7010 u8 q = *(u8 *) queue;
7022 static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
7024 struct ctlr_info *h = queue_to_hba((u8 *) queue);
7026 u8 q = *(u8 *) queue;
7041 static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
7043 struct ctlr_info *h = queue_to_hba(queue);
7045 u8 q = *(u8 *) queue;
7463 unsigned int queue, cpu;
7465 for (queue = 0; queue < h->msix_vectors; queue++) {
7466 mask = pci_irq_get_affinity(h->pdev, queue);
7471 h->reply_map[cpu] = queue;
7876 /* setup mapping between CPU and reply queue */
8058 /* Single reply queue, only one irq to free */
8086 * queue to process.
9272 /* initialize all reply queue entries to unused */