Lines Matching refs:r32
308 u32 r32;
313 r32 = readl(rb + FNC_PERS_REG);
314 r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc));
315 ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH;
325 u32 r32;
327 r32 = readl(rb + CT2_HOSTFN_PERSONALITY0);
328 ioc->port_id = ((r32 & __FC_LL_PORT_MAP__MK) >> __FC_LL_PORT_MAP__SH);
341 u32 r32, mode;
343 r32 = readl(rb + FNC_PERS_REG);
344 bfa_trc(ioc, r32);
346 mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) &
360 r32 &= ~(__F0_INTX_STATUS << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
361 r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
362 bfa_trc(ioc, r32);
364 writel(r32, rb + FNC_PERS_REG);
370 u32 r32;
372 r32 = readl(ioc->ioc_regs.lpu_read_stat);
373 if (r32) {
406 uint32_t r32 = readl(ioc->ioc_regs.ioc_fail_sync);
407 uint32_t sync_reqd = bfa_ioc_ct_get_sync_reqd(r32);
433 uint32_t r32 = readl(ioc->ioc_regs.ioc_fail_sync);
436 writel((r32 | sync_pos), ioc->ioc_regs.ioc_fail_sync);
442 uint32_t r32 = readl(ioc->ioc_regs.ioc_fail_sync);
446 writel((r32 & ~sync_msk), ioc->ioc_regs.ioc_fail_sync);
452 uint32_t r32 = readl(ioc->ioc_regs.ioc_fail_sync);
454 writel((r32 | bfa_ioc_ct_sync_pos(ioc)),
461 uint32_t r32 = readl(ioc->ioc_regs.ioc_fail_sync);
462 uint32_t sync_reqd = bfa_ioc_ct_get_sync_reqd(r32);
463 uint32_t sync_ackd = bfa_ioc_ct_get_sync_ackd(r32);
481 writel(bfa_ioc_ct_clear_sync_ackd(r32),
494 writel((r32 | sync_ackd), ioc->ioc_regs.ioc_fail_sync);
565 u32 r32;
567 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT);
568 if (r32 & __MSIX_VT_NUMVT__MK) {
569 writel(r32 & __MSIX_VT_OFST_,
584 u32 pll_sclk, pll_fclk, r32;
631 r32 = readl((rb + PSS_CTL_REG));
632 r32 &= ~__PSS_LMEM_RESET;
633 writel(r32, (rb + PSS_CTL_REG));
642 r32 = readl((rb + MBIST_STAT_REG));
650 u32 r32;
655 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
656 r32 &= ~(__APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN);
657 r32 |= (__APP_PLL_SCLK_ENARST | __APP_PLL_SCLK_BYPASS |
659 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
665 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
666 r32 &= ~(__APP_PLL_SCLK_REFCLK_SEL | __APP_PLL_SCLK_CLK_DIV2);
667 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
672 r32 = readl((rb + CT2_CHIP_MISC_PRG));
673 writel(r32 | __ETH_CLK_ENABLE_PORT0, (rb + CT2_CHIP_MISC_PRG));
675 r32 = readl((rb + CT2_PCIE_MISC_REG));
676 writel(r32 | __ETH_CLK_ENABLE_PORT1, (rb + CT2_PCIE_MISC_REG));
681 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
682 r32 &= (__P_SCLK_PLL_LOCK | __APP_PLL_SCLK_REFCLK_SEL |
684 writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG));
695 u32 r32;
700 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
701 r32 &= ~(__APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN);
702 r32 |= (__APP_PLL_LCLK_ENARST | __APP_PLL_LCLK_BYPASS |
704 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
709 r32 = readl((rb + CT2_CHIP_MISC_PRG));
710 writel(r32, (rb + CT2_CHIP_MISC_PRG));
715 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
716 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
721 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
722 r32 &= (__P_LCLK_PLL_LOCK | __APP_LPUCLK_HALFSPEED);
723 r32 |= 0x20c1731b;
724 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
735 u32 r32;
737 r32 = readl((rb + PSS_CTL_REG));
738 r32 &= ~__PSS_LMEM_RESET;
739 writel(r32, (rb + PSS_CTL_REG));
760 u32 r32;
762 r32 = readl((rb + PSS_GPIO_OUT_REG));
763 writel(r32 & ~1, (rb + PSS_GPIO_OUT_REG));
764 r32 = readl((rb + PSS_GPIO_OE_REG));
765 writel(r32 | 1, (rb + PSS_GPIO_OE_REG));
777 u32 r32;
779 r32 = readl(rb + CT2_NFC_CSR_SET_REG);
780 if (r32 & __NFC_CONTROLLER_HALTED)
803 u32 r32;
808 r32 = readl(rb + CT2_NFC_CSR_SET_REG);
809 if (!(r32 & __NFC_CONTROLLER_HALTED))
819 u32 r32;
827 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
828 writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
831 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
832 writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,
840 u32 r32, i;
842 r32 = readl((rb + PSS_CTL_REG));
843 r32 |= (__PSS_LPU0_RESET | __PSS_LPU1_RESET);
844 writel(r32, (rb + PSS_CTL_REG));
849 r32 = readl(rb + CT2_NFC_FLASH_STS_REG);
851 if ((r32 & __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS))
854 WARN_ON(!(r32 & __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS));
857 r32 = readl(rb + CT2_NFC_FLASH_STS_REG);
859 if (!(r32 & __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS))
862 WARN_ON((r32 & __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS));
864 r32 = readl(rb + CT2_CSI_FW_CTL_REG);
865 WARN_ON((r32 & __RESET_AND_START_SCLK_LCLK_PLLS));
871 u32 r32;
877 r32 = readl(rb + CT2_NFC_STS_REG);
878 if (r32 == CT2_NFC_STATE_RUNNING)
883 r32 = readl(rb + CT2_NFC_STS_REG);
884 WARN_ON(!(r32 == CT2_NFC_STATE_RUNNING));
890 u32 wgn, r32, nfc_ver;
932 r32 = readl(rb + CT2_CHIP_MISC_PRG);
933 writel((r32 & 0xfbffffff), (rb + CT2_CHIP_MISC_PRG));
944 r32 = readl(rb + HOST_SEM5_REG);
945 if (r32 & 0x1) {
946 r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
947 if (r32 == 1) {
951 r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));
952 if (r32 == 1) {