Lines Matching defs:data
799 ushort data[ASC_MC_SAVE_DATA_WSIZE];
813 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
815 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
822 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
823 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
825 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
827 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
831 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
833 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
839 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
840 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
845 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
847 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
849 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
851 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
853 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
855 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
857 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
859 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
861 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
863 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
865 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
867 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
869 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
1886 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
3554 * Display data transfer statistics.
3836 * The source data is assumed to be in little-endian order in memory
3863 * The source data is assumed to be in little-endian order in memory
3882 * The source data is assumed to be in little-endian order in LRAM
4118 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4119 (fw->data[1] << 8) | fw->data[0];
4121 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4484 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4485 (fw->data[1] << 8) | fw->data[0];
4486 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4984 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4985 (fw->data[1] << 8) | fw->data[0];
4986 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5472 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5473 (fw->data[1] << 8) | fw->data[0];
5474 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
8908 sum += wval; /* Checksum treats all EEPROM data as words. */
11605 struct eisa_scsi_data *data;
11608 data = kzalloc(sizeof(*data), GFP_KERNEL);
11609 if (!data)
11651 data->host[i] = shost;
11663 dev_set_drvdata(dev, data);
11667 kfree(data->host[0]);
11668 kfree(data->host[1]);
11669 kfree(data);
11677 struct eisa_scsi_data *data = dev_get_drvdata(dev);
11681 struct Scsi_Host *shost = data->host[i];
11689 kfree(data);