Lines Matching refs:NCR5380_write
104 * NCR5380_write(register, value) - write to the specific register
436 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
437 NCR5380_write(MODE_REG, MR_BASE);
438 NCR5380_write(TARGET_COMMAND_REG, 0);
439 NCR5380_write(SELECT_ENABLE_REG, 0);
738 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
793 NCR5380_write(MODE_REG, MR_BASE);
794 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
892 NCR5380_write(MODE_REG, MR_BASE);
898 NCR5380_write(SELECT_ENABLE_REG, 0);
908 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
994 NCR5380_write(TARGET_COMMAND_REG, 0);
1000 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask);
1001 NCR5380_write(MODE_REG, MR_ARBITRATE);
1018 NCR5380_write(MODE_REG, MR_BASE);
1022 NCR5380_write(MODE_REG, MR_BASE);
1036 NCR5380_write(MODE_REG, MR_BASE);
1046 NCR5380_write(INITIATOR_COMMAND_REG,
1066 NCR5380_write(MODE_REG, MR_BASE);
1067 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1078 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask | (1 << scmd_id(cmd)));
1086 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_BSY |
1088 NCR5380_write(MODE_REG, MR_BASE);
1094 NCR5380_write(SELECT_ENABLE_REG, 0);
1105 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA |
1139 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1147 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1169 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1184 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1201 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1269 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1291 NCR5380_write(OUTPUT_DATA_REG, *d);
1306 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA);
1308 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1311 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1314 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1319 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK);
1341 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1343 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1385 NCR5380_write(TARGET_COMMAND_REG,
1387 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST);
1389 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1410 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1428 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1431 NCR5380_write(INITIATOR_COMMAND_REG,
1436 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1453 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1509 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1510 NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE | MR_MONITOR_BSY |
1529 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1531 NCR5380_write(START_DMA_INITIATOR_RECEIVE_REG, 0);
1534 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA);
1536 NCR5380_write(START_DMA_SEND_REG, 0);
1719 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1721 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN |
1725 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1811 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1842 NCR5380_write(TARGET_COMMAND_REG, 0);
1848 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1862 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1873 NCR5380_write(TARGET_COMMAND_REG, 0);
1892 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1901 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1918 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1962 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
2033 NCR5380_write(MODE_REG, MR_BASE);
2051 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_BSY);
2055 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2058 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2076 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(PHASE_MSGIN));
2163 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK);
2167 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2326 NCR5380_write(MODE_REG, MR_BASE);
2327 NCR5380_write(TARGET_COMMAND_REG, 0);
2328 NCR5380_write(SELECT_ENABLE_REG, 0);