Lines Matching defs:status_reg_value
557 static int twa_check_bits(u32 status_reg_value)
561 if ((status_reg_value & TW_STATUS_EXPECTED_BITS) != TW_STATUS_EXPECTED_BITS)
563 if ((status_reg_value & TW_STATUS_UNEXPECTED_BITS) != 0)
903 static int twa_decode_bits(TW_Device_Extension *tw_dev, u32 status_reg_value)
908 if (status_reg_value & TW_STATUS_PCI_PARITY_ERROR) {
913 if (status_reg_value & TW_STATUS_PCI_ABORT) {
919 if (status_reg_value & TW_STATUS_QUEUE_ERROR) {
927 if (status_reg_value & TW_STATUS_MICROCONTROLLER_ERROR) {
942 u32 status_reg_value, response_que_value;
945 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
947 while (((status_reg_value & TW_STATUS_RESPONSE_QUEUE_EMPTY) == 0) && (count < TW_MAX_RESPONSE_DRAIN)) {
949 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1221 u32 status_reg_value;
1231 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1234 if (!(status_reg_value & TW_STATUS_VALID_INTERRUPT))
1244 if (twa_check_bits(status_reg_value)) {
1245 if (twa_decode_bits(tw_dev, status_reg_value)) {
1252 if (status_reg_value & TW_STATUS_HOST_INTERRUPT)
1256 if (status_reg_value & TW_STATUS_ATTENTION_INTERRUPT) {
1271 if (status_reg_value & TW_STATUS_COMMAND_INTERRUPT) {
1292 if (status_reg_value & TW_STATUS_RESPONSE_INTERRUPT) {
1295 while ((status_reg_value & TW_STATUS_RESPONSE_QUEUE_EMPTY) == 0) {
1364 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1365 if (twa_check_bits(status_reg_value)) {
1366 if (twa_decode_bits(tw_dev, status_reg_value)) {
1458 u32 status_reg_value;
1462 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1465 if (twa_check_bits(status_reg_value))
1466 twa_decode_bits(tw_dev, status_reg_value);
1468 while ((status_reg_value & flag) != flag) {
1469 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1471 if (twa_check_bits(status_reg_value))
1472 twa_decode_bits(tw_dev, status_reg_value);
1487 u32 status_reg_value;
1491 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1494 if (twa_check_bits(status_reg_value))
1495 twa_decode_bits(tw_dev, status_reg_value);
1497 while ((status_reg_value & flag) != 0) {
1498 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1499 if (twa_check_bits(status_reg_value))
1500 twa_decode_bits(tw_dev, status_reg_value);
1515 u32 status_reg_value;
1528 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1530 if (twa_check_bits(status_reg_value))
1531 twa_decode_bits(tw_dev, status_reg_value);
1533 if (((tw_dev->pending_request_count > 0) && (tw_dev->state[request_id] != TW_S_PENDING)) || (status_reg_value & TW_STATUS_COMMAND_QUEUE_FULL)) {