Lines Matching refs:base
142 void __iomem *base;
151 val = readl(chip->base + SUNXI_ALRM_IRQ_STA);
155 writel(val, chip->base + SUNXI_ALRM_IRQ_STA);
171 alrm_val = readl(chip->base + SUNXI_ALRM_EN);
174 alrm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN);
178 chip->base + SUNXI_ALRM_IRQ_STA);
181 writel(alrm_val, chip->base + SUNXI_ALRM_EN);
182 writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN);
193 alrm = readl(chip->base + SUNXI_ALRM_DHMS);
194 date = readl(chip->base + SUNXI_RTC_YMD);
213 alrm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN);
229 date = readl(chip->base + SUNXI_RTC_YMD);
230 time = readl(chip->base + SUNXI_RTC_HMS);
231 } while ((date != readl(chip->base + SUNXI_RTC_YMD)) ||
232 (time != readl(chip->base + SUNXI_RTC_HMS)));
293 writel(0, chip->base + SUNXI_ALRM_DHMS);
300 writel(alrm, chip->base + SUNXI_ALRM_DHMS);
302 writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
303 writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN);
317 reg = readl(chip->base + offset);
363 writel(0, chip->base + SUNXI_RTC_HMS);
364 writel(0, chip->base + SUNXI_RTC_YMD);
366 writel(time, chip->base + SUNXI_RTC_HMS);
380 writel(date, chip->base + SUNXI_RTC_YMD);
438 chip->base = devm_platform_ioremap_resource(pdev, 0);
439 if (IS_ERR(chip->base))
440 return PTR_ERR(chip->base);
459 writel(0, chip->base + SUNXI_ALRM_DHMS);
462 writel(0, chip->base + SUNXI_ALRM_EN);
465 writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
468 writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base +