Lines Matching defs:rtc
16 #include <linux/rtc.h>
114 void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags);
133 static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
135 const struct stm32_rtc_registers *regs = &rtc->data->regs;
137 writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr);
138 writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr);
141 static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
143 const struct stm32_rtc_registers *regs = &rtc->data->regs;
145 writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr);
148 static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
150 const struct stm32_rtc_registers *regs = &rtc->data->regs;
151 unsigned int isr = readl_relaxed(rtc->base + regs->isr);
155 writel_relaxed(isr, rtc->base + regs->isr);
164 rtc->base + regs->isr,
172 static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
174 const struct stm32_rtc_registers *regs = &rtc->data->regs;
175 unsigned int isr = readl_relaxed(rtc->base + regs->isr);
178 writel_relaxed(isr, rtc->base + regs->isr);
181 static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
183 const struct stm32_rtc_registers *regs = &rtc->data->regs;
184 unsigned int isr = readl_relaxed(rtc->base + regs->isr);
187 writel_relaxed(isr, rtc->base + regs->isr);
193 return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
199 static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc,
202 rtc->data->clear_events(rtc, flags);
207 struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
208 const struct stm32_rtc_registers *regs = &rtc->data->regs;
209 const struct stm32_rtc_events *evts = &rtc->data->events;
212 mutex_lock(&rtc->rtc_dev->ops_lock);
214 status = readl_relaxed(rtc->base + regs->sr);
215 cr = readl_relaxed(rtc->base + regs->cr);
220 dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
223 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
226 stm32_rtc_clear_event_flags(rtc, evts->alra);
229 mutex_unlock(&rtc->rtc_dev->ops_lock);
247 * - on rtc side, 0=invalid,1=Monday...7=Sunday
265 * - on rtc side, 0=invalid,1=Monday...7=Sunday
272 struct stm32_rtc *rtc = dev_get_drvdata(dev);
273 const struct stm32_rtc_registers *regs = &rtc->data->regs;
277 tr = readl_relaxed(rtc->base + regs->tr);
278 dr = readl_relaxed(rtc->base + regs->dr);
298 struct stm32_rtc *rtc = dev_get_drvdata(dev);
299 const struct stm32_rtc_registers *regs = &rtc->data->regs;
316 stm32_rtc_wpr_unlock(rtc);
318 ret = stm32_rtc_enter_init_mode(rtc);
324 writel_relaxed(tr, rtc->base + regs->tr);
325 writel_relaxed(dr, rtc->base + regs->dr);
327 stm32_rtc_exit_init_mode(rtc);
329 ret = stm32_rtc_wait_sync(rtc);
331 stm32_rtc_wpr_lock(rtc);
338 struct stm32_rtc *rtc = dev_get_drvdata(dev);
339 const struct stm32_rtc_registers *regs = &rtc->data->regs;
340 const struct stm32_rtc_events *evts = &rtc->data->events;
344 alrmar = readl_relaxed(rtc->base + regs->alrmar);
345 cr = readl_relaxed(rtc->base + regs->cr);
346 status = readl_relaxed(rtc->base + regs->sr);
406 struct stm32_rtc *rtc = dev_get_drvdata(dev);
407 const struct stm32_rtc_registers *regs = &rtc->data->regs;
408 const struct stm32_rtc_events *evts = &rtc->data->events;
411 cr = readl_relaxed(rtc->base + regs->cr);
413 stm32_rtc_wpr_unlock(rtc);
420 writel_relaxed(cr, rtc->base + regs->cr);
423 stm32_rtc_clear_event_flags(rtc, evts->alra);
425 stm32_rtc_wpr_lock(rtc);
430 static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm)
432 const struct stm32_rtc_registers *regs = &rtc->data->regs;
434 unsigned int dr = readl_relaxed(rtc->base + regs->dr);
435 unsigned int tr = readl_relaxed(rtc->base + regs->tr);
468 struct stm32_rtc *rtc = dev_get_drvdata(dev);
469 const struct stm32_rtc_registers *regs = &rtc->data->regs;
480 if (stm32_rtc_valid_alrm(rtc, tm) < 0) {
498 stm32_rtc_wpr_unlock(rtc);
501 cr = readl_relaxed(rtc->base + regs->cr);
503 writel_relaxed(cr, rtc->base + regs->cr);
509 ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
520 writel_relaxed(alrmar, rtc->base + regs->alrmar);
524 stm32_rtc_wpr_lock(rtc);
537 static void stm32_rtc_clear_events(struct stm32_rtc *rtc,
540 const struct stm32_rtc_registers *regs = &rtc->data->regs;
543 writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags,
544 rtc->base + regs->isr);
591 static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc,
594 struct stm32_rtc_registers regs = rtc->data->regs;
597 writel_relaxed(flags, rtc->base + regs.scr);
623 { .compatible = "st,stm32-rtc", .data = &stm32_rtc_data },
624 { .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data },
625 { .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data },
631 struct stm32_rtc *rtc)
633 const struct stm32_rtc_registers *regs = &rtc->data->regs;
638 rate = clk_get_rate(rtc->rtc_ck);
664 stm32_rtc_wpr_unlock(rtc);
666 ret = stm32_rtc_enter_init_mode(rtc);
674 writel_relaxed(prer, rtc->base + regs->prer);
676 writel_relaxed(prer, rtc->base + regs->prer);
679 cr = readl_relaxed(rtc->base + regs->cr);
681 writel_relaxed(cr, rtc->base + regs->cr);
683 stm32_rtc_exit_init_mode(rtc);
685 ret = stm32_rtc_wait_sync(rtc);
687 stm32_rtc_wpr_lock(rtc);
694 struct stm32_rtc *rtc;
698 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
699 if (!rtc)
702 rtc->base = devm_platform_ioremap_resource(pdev, 0);
703 if (IS_ERR(rtc->base))
704 return PTR_ERR(rtc->base);
706 rtc->data = (struct stm32_rtc_data *)
708 regs = &rtc->data->regs;
710 if (rtc->data->need_dbp) {
711 rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
713 if (IS_ERR(rtc->dbp)) {
715 return PTR_ERR(rtc->dbp);
719 1, &rtc->dbp_reg);
726 2, &rtc->dbp_mask);
733 if (!rtc->data->has_pclk) {
734 rtc->pclk = NULL;
735 rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL);
737 rtc->pclk = devm_clk_get(&pdev->dev, "pclk");
738 if (IS_ERR(rtc->pclk)) {
740 return PTR_ERR(rtc->pclk);
742 rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck");
744 if (IS_ERR(rtc->rtc_ck)) {
746 return PTR_ERR(rtc->rtc_ck);
749 if (rtc->data->has_pclk) {
750 ret = clk_prepare_enable(rtc->pclk);
755 ret = clk_prepare_enable(rtc->rtc_ck);
759 if (rtc->data->need_dbp)
760 regmap_update_bits(rtc->dbp, rtc->dbp_reg,
761 rtc->dbp_mask, rtc->dbp_mask);
771 ret = stm32_rtc_init(pdev, rtc);
775 rtc->irq_alarm = platform_get_irq(pdev, 0);
776 if (rtc->irq_alarm <= 0) {
777 ret = rtc->irq_alarm;
782 if (rtc->data->has_wakeirq) {
783 rtc->wakeirq_alarm = platform_get_irq(pdev, 1);
784 if (rtc->wakeirq_alarm > 0) {
786 rtc->wakeirq_alarm);
788 ret = rtc->wakeirq_alarm;
789 if (rtc->wakeirq_alarm == -EPROBE_DEFER)
796 platform_set_drvdata(pdev, rtc);
798 rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
800 if (IS_ERR(rtc->rtc_dev)) {
801 ret = PTR_ERR(rtc->rtc_dev);
802 dev_err(&pdev->dev, "rtc device registration failed, err=%d\n",
808 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL,
810 pdev->name, rtc);
813 rtc->irq_alarm);
821 if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS))
825 u32 ver = readl_relaxed(rtc->base + regs->verr);
835 clk_disable_unprepare(rtc->rtc_ck);
837 if (rtc->data->has_pclk)
838 clk_disable_unprepare(rtc->pclk);
840 if (rtc->data->need_dbp)
841 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
851 struct stm32_rtc *rtc = platform_get_drvdata(pdev);
852 const struct stm32_rtc_registers *regs = &rtc->data->regs;
856 stm32_rtc_wpr_unlock(rtc);
857 cr = readl_relaxed(rtc->base + regs->cr);
859 writel_relaxed(cr, rtc->base + regs->cr);
860 stm32_rtc_wpr_lock(rtc);
862 clk_disable_unprepare(rtc->rtc_ck);
863 if (rtc->data->has_pclk)
864 clk_disable_unprepare(rtc->pclk);
867 if (rtc->data->need_dbp)
868 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
879 struct stm32_rtc *rtc = dev_get_drvdata(dev);
881 if (rtc->data->has_pclk)
882 clk_disable_unprepare(rtc->pclk);
885 return enable_irq_wake(rtc->irq_alarm);
892 struct stm32_rtc *rtc = dev_get_drvdata(dev);
895 if (rtc->data->has_pclk) {
896 ret = clk_prepare_enable(rtc->pclk);
901 ret = stm32_rtc_wait_sync(rtc);
903 if (rtc->data->has_pclk)
904 clk_disable_unprepare(rtc->pclk);
909 return disable_irq_wake(rtc->irq_alarm);