Lines Matching refs:pxa_rtc
71 #define rtc_readl(pxa_rtc, reg) \
72 __raw_readl((pxa_rtc)->base + (reg))
73 #define rtc_writel(pxa_rtc, reg, value) \
74 __raw_writel((value), (pxa_rtc)->base + (reg))
76 struct pxa_rtc {
112 static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
116 rtsr = rtc_readl(pxa_rtc, RTSR);
119 rtc_writel(pxa_rtc, RTSR, rtsr);
122 static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
126 rtsr = rtc_readl(pxa_rtc, RTSR);
129 rtc_writel(pxa_rtc, RTSR, rtsr);
134 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev_id);
138 spin_lock(&pxa_rtc->lock);
141 rtsr = rtc_readl(pxa_rtc, RTSR);
142 rtc_writel(pxa_rtc, RTSR, rtsr);
145 rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);
159 rtc_update_irq(pxa_rtc->rtc, 1, events);
162 rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
164 spin_unlock(&pxa_rtc->lock);
170 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
173 ret = request_irq(pxa_rtc->sa1100_rtc.irq_1hz, pxa_rtc_irq, 0,
177 pxa_rtc->sa1100_rtc.irq_1hz, ret);
180 ret = request_irq(pxa_rtc->sa1100_rtc.irq_alarm, pxa_rtc_irq, 0,
184 pxa_rtc->sa1100_rtc.irq_alarm, ret);
191 free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
198 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
200 spin_lock_irq(&pxa_rtc->lock);
201 rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
202 spin_unlock_irq(&pxa_rtc->lock);
204 free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
205 free_irq(pxa_rtc->sa1100_rtc.irq_alarm, dev);
210 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
212 spin_lock_irq(&pxa_rtc->lock);
215 rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
217 rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
219 spin_unlock_irq(&pxa_rtc->lock);
225 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
228 rycr = rtc_readl(pxa_rtc, RYCR);
229 rdcr = rtc_readl(pxa_rtc, RDCR);
237 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
239 rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
240 rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
247 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
250 ryar = rtc_readl(pxa_rtc, RYAR1);
251 rdar = rtc_readl(pxa_rtc, RDAR1);
254 rtsr = rtc_readl(pxa_rtc, RTSR);
262 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
265 spin_lock_irq(&pxa_rtc->lock);
267 rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
268 rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));
270 rtsr = rtc_readl(pxa_rtc, RTSR);
275 rtc_writel(pxa_rtc, RTSR, rtsr);
277 spin_unlock_irq(&pxa_rtc->lock);
284 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
286 seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
288 (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
290 (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
291 seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));
308 struct pxa_rtc *pxa_rtc;
312 pxa_rtc = devm_kzalloc(dev, sizeof(*pxa_rtc), GFP_KERNEL);
313 if (!pxa_rtc)
315 sa1100_rtc = &pxa_rtc->sa1100_rtc;
317 spin_lock_init(&pxa_rtc->lock);
318 platform_set_drvdata(pdev, pxa_rtc);
320 pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
321 if (!pxa_rtc->ress) {
337 pxa_rtc->base = devm_ioremap(dev, pxa_rtc->ress->start,
338 resource_size(pxa_rtc->ress));
339 if (!pxa_rtc->base) {
346 sa1100_rtc->rcnr = pxa_rtc->base + 0x0;
347 sa1100_rtc->rtsr = pxa_rtc->base + 0x8;
348 sa1100_rtc->rtar = pxa_rtc->base + 0x4;
349 sa1100_rtc->rttr = pxa_rtc->base + 0xc;
356 rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
358 pxa_rtc->rtc = devm_rtc_device_register(&pdev->dev, "pxa-rtc",
360 if (IS_ERR(pxa_rtc->rtc)) {
361 ret = PTR_ERR(pxa_rtc->rtc);
390 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
393 enable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
399 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
402 disable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);