Lines Matching defs:rtc
16 #include <linux/rtc.h>
57 struct rtc_device *rtc;
64 static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
66 return readl(rtc->base + reg);
69 static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
75 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
81 static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
86 ret = jz4740_rtc_wait_write_ready(rtc);
90 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
93 ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
99 static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
104 if (rtc->type >= ID_JZ4760)
105 ret = jz4780_rtc_enable_write(rtc);
107 ret = jz4740_rtc_wait_write_ready(rtc);
109 writel(val, rtc->base + reg);
114 static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
121 spin_lock_irqsave(&rtc->lock, flags);
123 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
133 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
135 spin_unlock_irqrestore(&rtc->lock, flags);
142 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
146 if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
153 secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
154 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
158 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
171 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
174 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
178 return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
183 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
187 secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
189 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
202 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
205 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
207 ret = jz4740_rtc_ctrl_set_bits(rtc,
215 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
216 return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
229 struct jz4740_rtc *rtc = data;
233 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
241 rtc_update_irq(rtc->rtc, 1, events);
243 jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
250 struct jz4740_rtc *rtc = dev_get_drvdata(dev);
251 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
266 { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
267 { .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 },
268 { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
273 static void jz4740_rtc_set_wakeup_params(struct jz4740_rtc *rtc,
295 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_WAKEUP_FILTER, wakeup_ticks);
306 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_RESET_COUNTER, reset_ticks);
313 struct jz4740_rtc *rtc;
318 rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
319 if (!rtc)
322 rtc->type = (enum jz4740_rtc_type)device_get_match_data(dev);
328 rtc->base = devm_platform_ioremap_resource(pdev, 0);
329 if (IS_ERR(rtc->base))
330 return PTR_ERR(rtc->base);
332 clk = devm_clk_get(dev, "rtc");
350 spin_lock_init(&rtc->lock);
352 platform_set_drvdata(pdev, rtc);
362 rtc->rtc = devm_rtc_allocate_device(dev);
363 if (IS_ERR(rtc->rtc)) {
364 ret = PTR_ERR(rtc->rtc);
365 dev_err(dev, "Failed to allocate rtc device: %d\n", ret);
369 rtc->rtc->ops = &jz4740_rtc_ops;
370 rtc->rtc->range_max = U32_MAX;
373 jz4740_rtc_set_wakeup_params(rtc, np, rate);
376 jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1);
378 ret = rtc_register_device(rtc->rtc);
383 pdev->name, rtc);
385 dev_err(dev, "Failed to request rtc irq: %d\n", ret);
404 .name = "jz4740-rtc",
414 MODULE_ALIAS("platform:jz4740-rtc");